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Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vtTfY-0000000FJyC-2jRF; Fri, 20 Feb 2026 16:47:56 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vtTfW-0000000FJxL-0HOW for linux-arm-kernel@lists.infradead.org; Fri, 20 Feb 2026 16:47:55 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E5D85339; Fri, 20 Feb 2026 08:47:46 -0800 (PST) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 357F23F62B; Fri, 20 Feb 2026 08:47:52 -0800 (PST) Date: Fri, 20 Feb 2026 16:47:49 +0000 From: Catalin Marinas To: "David Hildenbrand (Arm)" Cc: linux-arm-kernel@lists.infradead.org, Mark Brown , Will Deacon , Emanuele Rocca , Mark Rutland Subject: Re: [PATCH 1/3] arm64: gcs: Do not set PTE_SHARED on GCS mappings if FEAT_LPA2 is enabled Message-ID: References: <20260220140532.285011-1-catalin.marinas@arm.com> <20260220140532.285011-2-catalin.marinas@arm.com> <42e1608b-5a01-4f9c-992f-a1d3a3e54f99@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260220_084754_146151_094A7662 X-CRM114-Status: GOOD ( 21.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Feb 20, 2026 at 04:45:11PM +0000, Catalin Marinas wrote: > On Fri, Feb 20, 2026 at 04:56:26PM +0100, David Hildenbrand wrote: > > On 2/20/26 15:05, Catalin Marinas wrote: > > > diff --git a/arch/arm64/include/asm/pgtable-prot.h b/arch/arm64/include/asm/pgtable-prot.h > > > index 161e8660eddd..a65f2c50e9ca 100644 > > > --- a/arch/arm64/include/asm/pgtable-prot.h > > > +++ b/arch/arm64/include/asm/pgtable-prot.h > > > @@ -164,8 +164,8 @@ static inline bool __pure lpa2_is_enabled(void) > > > #define _PAGE_GCS (_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_WRITE | PTE_USER) > > > #define _PAGE_GCS_RO (_PAGE_DEFAULT | PTE_NG | PTE_UXN | PTE_USER) > > > -#define PAGE_GCS __pgprot(_PAGE_GCS) > > > -#define PAGE_GCS_RO __pgprot(_PAGE_GCS_RO) > > > +#define PAGE_GCS __pgprot((_PAGE_GCS & ~PTE_SHARED) | PTE_MAYBE_SHARED) > > > +#define PAGE_GCS_RO __pgprot((_PAGE_GCS_RO & ~PTE_SHARED) | PTE_MAYBE_SHARED) > > > #define PIE_E0 ( \ > > > PIRx_ELx_PERM_PREP(pte_pi_index(_PAGE_GCS), PIE_GCS) | \ > > > diff --git a/arch/arm64/mm/mmap.c b/arch/arm64/mm/mmap.c > > > index 08ee177432c2..2e404441063b 100644 > > > --- a/arch/arm64/mm/mmap.c > > > +++ b/arch/arm64/mm/mmap.c > > > @@ -87,7 +87,7 @@ pgprot_t vm_get_page_prot(vm_flags_t vm_flags) > > > /* Short circuit GCS to avoid bloating the table. */ > > > if (system_supports_gcs() && (vm_flags & VM_SHADOW_STACK)) { > > > - prot = _PAGE_GCS_RO; > > > + prot = pgprot_val(PAGE_GCS_RO); > > > } else { > > > prot = pgprot_val(protection_map[vm_flags & > > > (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]); > > > > The only confusion I have is why we don't update _PAGE_GCS/_PAGE_GCS_RO, > > consequently leaving PTE_SHARED set for the other users of > > _PAGE_GCS/_PAGE_GCS_RO in arch/arm64/include/asm/pgtable-prot.h. > > > > Staring at pte_pi_index() (and the definitions of PTE_PI_IDX_0), I assume it > > doesn't matter. > > > > Just curious why we don't fixup _PAGE_GCS / _PAGE_GCS_RO instead. > > _PAGE_GCS needs to be constant as it ends up in asm, so we can't add > the dynamic PTE_MAYBE_SHARED. There are other ways to solve this but it > is somewhat more consistent with the other _PAGE_* definitions which all > have PTE_SHARED. Hmm, it's only in asm-offsets and it looks like the compiler didn't complain. I'll check the generated code. -- Catalin