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([2a02:168:6806:0:3f02:d36b:e22e:74c6]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3d53fda847dsm10118932f8f.0.2025.09.02.03.33.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Sep 2025 03:33:10 -0700 (PDT) Message-ID: Subject: Re: [Bug 220479] New: [regression 6.16] mvebu: no pci devices detected on turris omnia From: Klaus Kudielka To: Jan Palus , Rob Herring Cc: Bjorn Helgaas , Thomas Petazzoni , Pali =?ISO-8859-1?Q?Roh=E1r?= , linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, regressions@lists.linux.dev Date: Tue, 02 Sep 2025 12:33:09 +0200 In-Reply-To: <1cc6781ea584aa00a8cda23db1fc8cd59f852a3d.camel@gmail.com> References: <20250820184603.GA633069@bhelgaas> <42rznc7krv3gdwmdzfz6o5nalnzleiwfg44yleqjet67cu4ijm@pwap3ph2n2u7> <1cc6781ea584aa00a8cda23db1fc8cd59f852a3d.camel@gmail.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2-2+b1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20250902_033312_864712_C7DD2B7D X-CRM114-Status: GOOD ( 13.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, 2025-09-02 at 11:09 +0200, Klaus Kudielka wrote: > Something like this on top of mainline - completely untested, but maybe w= orth a try. >=20 > diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/= pci-mvebu.c > index 755651f338..3fce4a2b63 100644 > --- a/drivers/pci/controller/pci-mvebu.c > +++ b/drivers/pci/controller/pci-mvebu.c > @@ -1168,9 +1168,6 @@ static void __iomem *mvebu_pcie_map_registers(struc= t platform_device *pdev, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return devm_ioremap_resource(&= pdev->dev, &port->regs); > =C2=A0} > =C2=A0 > -#define DT_FLAGS_TO_TYPE(flags)=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (((f= lags) >> 24) & 0x03) > -#define=C2=A0=C2=A0=C2=A0 DT_TYPE_IO=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x1 > -#define=C2=A0=C2=A0=C2=A0 DT_TYPE_MEM32=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 0x2 > =C2=A0#define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF) > =C2=A0#define DT_CPUADDR_TO_ATTR(cpuaddr)=C2=A0=C2=A0 (((cpuaddr) >> 48) = & 0xFF) > =C2=A0 > @@ -1189,17 +1186,9 @@ static int mvebu_get_tgt_attr(struct device_node *= np, int devfn, > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 return -EINVAL; > =C2=A0 > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 for_each_of_range(&parser, &ra= nge) { > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 unsigned long rtype; > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 u32 slot =3D upper_32_bits(range.bus_addr); > =C2=A0 > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 if (DT_FLAGS_TO_TYPE(range.flags) =3D=3D DT_TYPE_IO) > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtype =3D IORE= SOURCE_IO; > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 else if (DT_FLAGS_TO_TYPE(range.flags) =3D=3D DT_TYPE_MEM32) > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 rtype =3D IORE= SOURCE_MEM; > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 else > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 continue; > - > -=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 if (slot =3D=3D PCI_SLOT(devfn) && type =3D=3D rtype) { > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 if (slot =3D=3D PCI_SLOT(devfn) && type =3D=3D range.flags) { > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *tgt =3D= DT_CPUADDR_TO_TARGET(range.cpu_addr); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 *attr = =3D DT_CPUADDR_TO_ATTR(range.cpu_addr); > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return 0= ; >=20 Following up myself. With this patch on top of 6.17.0-rc4, I do see the PCI= bridges for the two free slots on my Turris Omnia. One slot is occupied by mSATA. I don't have any suitable Mini-PCIe card to = test, though. $ lspci 00:02.0 PCI bridge: Marvell Technology Group Ltd. 88F6820 [Armada 385] ARM = SoC (rev 04) 00:03.0 PCI bridge: Marvell Technology Group Ltd. 88F6820 [Armada 385] ARM = SoC (rev 04) $ dmesg | head -5 [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 6.17.0-rc4+ (klaus@mars) (arm-linux-gnueabihf-= gcc (Debian 14.3.0-5) 14.3.0, GNU ld (GNU Binutils for Debian) 2.45) #10 SM= P Tue Sep 2 11:49:13 CEST 2025 [ 0.000000] CPU: ARMv7 Processor [414fc091] revision 1 (ARMv7), cr=3D10c= 5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instr= uction cache [ 0.000000] OF: fdt: Machine model: Turris Omnia $ dmesg | grep -i pci [ 0.015195] PCI: CLS 0 bytes, default 64 [ 0.026199] mvebu-pcie soc:pcie: host bridge /soc/pcie ranges: [ 0.026224] mvebu-pcie soc:pcie: MEM 0x00f1080000..0x00f1081fff -> = 0x0000080000 [ 0.026240] mvebu-pcie soc:pcie: MEM 0x00f1040000..0x00f1041fff -> = 0x0000040000 [ 0.026253] mvebu-pcie soc:pcie: MEM 0x00f1044000..0x00f1045fff -> = 0x0000044000 [ 0.026265] mvebu-pcie soc:pcie: MEM 0x00f1048000..0x00f1049fff -> = 0x0000048000 [ 0.026278] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00ffffff= fe -> 0x0100000000 [ 0.026290] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00ffffff= fe -> 0x0100000000 [ 0.026302] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00ffffff= fe -> 0x0200000000 [ 0.026314] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00ffffff= fe -> 0x0200000000 [ 0.026326] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00ffffff= fe -> 0x0300000000 [ 0.026338] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00ffffff= fe -> 0x0300000000 [ 0.026350] mvebu-pcie soc:pcie: MEM 0xffffffffffffffff..0x00ffffff= fe -> 0x0400000000 [ 0.026358] mvebu-pcie soc:pcie: IO 0xffffffffffffffff..0x00ffffff= fe -> 0x0400000000 [ 0.026554] mvebu-pcie soc:pcie: pcie1.0: Slot power limit 10.0W [ 0.026743] mvebu-pcie soc:pcie: pcie2.0: Slot power limit 10.0W [ 0.026955] mvebu-pcie soc:pcie: PCI host bridge to bus 0000:00 [ 0.026963] pci_bus 0000:00: root bus resource [bus 00-ff] [ 0.026970] pci_bus 0000:00: root bus resource [mem 0xf1080000-0xf1081ff= f] (bus address [0x00080000-0x00081fff]) [ 0.026976] pci_bus 0000:00: root bus resource [mem 0xf1040000-0xf1041ff= f] (bus address [0x00040000-0x00041fff]) [ 0.026981] pci_bus 0000:00: root bus resource [mem 0xf1044000-0xf1045ff= f] (bus address [0x00044000-0x00045fff]) [ 0.026986] pci_bus 0000:00: root bus resource [mem 0xf1048000-0xf1049ff= f] (bus address [0x00048000-0x00049fff]) [ 0.026991] pci_bus 0000:00: root bus resource [mem 0xe0000000-0xe7fffff= f] [ 0.026995] pci_bus 0000:00: root bus resource [io 0x1000-0xeffff] [ 0.027113] pci 0000:00:02.0: [11ab:6820] type 01 class 0x060400 PCIe Ro= ot Port [ 0.027127] pci 0000:00:02.0: PCI bridge to [bus 00] [ 0.027134] pci 0000:00:02.0: bridge window [io 0x0000-0x0fff] [ 0.027138] pci 0000:00:02.0: bridge window [mem 0x00000000-0x000fffff= ] [ 0.027277] /soc/pcie/pcie@2,0: Fixed dependency cycle(s) with /soc/pcie= /pcie@2,0/interrupt-controller [ 0.027311] pci 0000:00:03.0: [11ab:6820] type 01 class 0x060400 PCIe Ro= ot Port [ 0.027323] pci 0000:00:03.0: PCI bridge to [bus 00] [ 0.027329] pci 0000:00:03.0: bridge window [io 0x0000-0x0fff] [ 0.027333] pci 0000:00:03.0: bridge window [mem 0x00000000-0x000fffff= ] [ 0.027443] /soc/pcie/pcie@3,0: Fixed dependency cycle(s) with /soc/pcie= /pcie@3,0/interrupt-controller [ 0.028311] PCI: bus0: Fast back to back transfers disabled [ 0.028319] pci 0000:00:02.0: bridge configuration invalid ([bus 00-00])= , reconfiguring [ 0.028327] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00])= , reconfiguring [ 0.028418] PCI: bus1: Fast back to back transfers enabled [ 0.028424] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01 [ 0.028506] PCI: bus2: Fast back to back transfers enabled [ 0.028510] pci_bus 0000:02: busn_res: [bus 02-ff] end is updated to 02 [ 0.028526] pci 0000:00:02.0: PCI bridge to [bus 01] [ 0.028535] pci 0000:00:03.0: PCI bridge to [bus 02] [ 0.028542] pci_bus 0000:00: resource 4 [mem 0xf1080000-0xf1081fff] [ 0.028547] pci_bus 0000:00: resource 5 [mem 0xf1040000-0xf1041fff] [ 0.028552] pci_bus 0000:00: resource 6 [mem 0xf1044000-0xf1045fff] [ 0.028556] pci_bus 0000:00: resource 7 [mem 0xf1048000-0xf1049fff] [ 0.028560] pci_bus 0000:00: resource 8 [mem 0xe0000000-0xe7ffffff] [ 0.028564] pci_bus 0000:00: resource 9 [io 0x1000-0xeffff]