From: Mark Rutland <mark.rutland@arm.com>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Ryan Roberts <ryan.roberts@arm.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64/mm: Describe TTBR1_BADDR_4852_OFFSET
Date: Thu, 26 Feb 2026 11:53:37 +0000 [thread overview]
Message-ID: <aaA0QbVbAvrCJ1QV@J2N7QTR9R3> (raw)
In-Reply-To: <20260225064028.1525192-1-anshuman.khandual@arm.com>
On Wed, Feb 25, 2026 at 06:40:28AM +0000, Anshuman Khandual wrote:
> TTBR1_BADDR_4852_OFFSET is a constant offset which gets added into kernel
> page table physical address for TTBR1_EL1 when kernel is build for 52 bit
> VA but found to be running on 48 bit VA capable system. Although there is
> no explanation on how the macro is computed.
>
> Describe TTBR1_BADDR_4852_OFFSET computation in detail via deriving from
> all required parameters involved thus improving clarity and readability.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Ryan Roberts <ryan.roberts@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> This applies on v7.0-rc1
>
> Earlier context can be found here.
>
> https://lore.kernel.org/linux-arm-kernel/aRb8ezhQd0c0jp9G@J2N7QTR9R3/
As with my comments last time, I have no strong feelings on this either
way; I'll leave it to Cataln and Will.
Mark.
> arch/arm64/include/asm/pgtable-hwdef.h | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index 5e6809a462c7..72f31800c703 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -285,9 +285,12 @@
> #endif
>
> #ifdef CONFIG_ARM64_VA_BITS_52
> +#define PTRS_PER_PGD_52_VA (UL(1) << (52 - PGDIR_SHIFT))
> +#define PTRS_PER_PGD_48_VA (UL(1) << (48 - PGDIR_SHIFT))
> +#define PTRS_PER_PGD_EXTRA (PTRS_PER_PGD_52_VA - PTRS_PER_PGD_48_VA)
> +
> /* Must be at least 64-byte aligned to prevent corruption of the TTBR */
> -#define TTBR1_BADDR_4852_OFFSET (((UL(1) << (52 - PGDIR_SHIFT)) - \
> - (UL(1) << (48 - PGDIR_SHIFT))) * 8)
> +#define TTBR1_BADDR_4852_OFFSET (PTRS_PER_PGD_EXTRA << PTDESC_ORDER)
> #endif
>
> #endif
> --
> 2.30.2
>
next prev parent reply other threads:[~2026-02-26 11:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-02-25 6:40 [PATCH] arm64/mm: Describe TTBR1_BADDR_4852_OFFSET Anshuman Khandual
2026-02-26 11:53 ` Mark Rutland [this message]
2026-03-27 19:20 ` Catalin Marinas
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