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Fri, 27 Feb 2026 14:42:08 -0800 (PST) Received: from geday ([2804:7f2:800b:feb1::dead:c001]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-94df6577a4fsm6403120241.10.2026.02.27.14.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Feb 2026 14:42:07 -0800 (PST) Date: Fri, 27 Feb 2026 19:42:01 -0300 From: Geraldo Nascimento To: Charalampos Mitrodimas Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , Dragan Simic , linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 1/4] PCI: rockchip: drop 2.5 GT/s defines Message-ID: References: <5172389ba8d291fe05bc0887bc97fe73f110c5c0.1772169998.git.geraldogabriel@gmail.com> <878qceku1j.fsf@posteo.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <878qceku1j.fsf@posteo.net> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260227_144209_740783_9AF20CB5 X-CRM114-Status: GOOD ( 25.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Charalampos, On Fri, Feb 27, 2026 at 04:53:00PM +0000, Charalampos Mitrodimas wrote: > Geraldo Nascimento writes: > > > Drop the 2.5 GT/s Link Speed defines from Rockchip PCIe header > > definitions. The reason is that Shawn Lin from Rockchip has > > reiterated that there may be danger of "catastrophic failure" > > in using their PCIe with 5.0 GT/s speeds. > > > > While Rockchip has done so informally without issuing a proper > > errata, and the particulars are thus unknown, this may cause > > data loss or worse. > > > > This change is corroborated by RK3399 official datasheet [1], which > > states maximum link speed for this platform is 2.5 GT/s. > > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf > > > > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") > > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ > > Cc: stable@vger.kernel.org > > Reported-by: Dragan Simic > > Reported-by: Shawn Lin > > Signed-off-by: Geraldo Nascimento > > --- > > drivers/pci/controller/pcie-rockchip.h | 3 --- > > 1 file changed, 3 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h > > index 3e82a69b9c00..b5da15601b58 100644 > > --- a/drivers/pci/controller/pcie-rockchip.h > > +++ b/drivers/pci/controller/pcie-rockchip.h > > @@ -42,7 +42,6 @@ > > #define PCIE_CLIENT_MODE_RC HWORD_SET_BIT(0x0040) > > #define PCIE_CLIENT_MODE_EP HWORD_CLR_BIT(0x0040) > > #define PCIE_CLIENT_GEN_SEL_1 HWORD_CLR_BIT(0x0080) > > -#define PCIE_CLIENT_GEN_SEL_2 HWORD_SET_BIT(0x0080) > > This commit alone won't compile right? PCIE_CLIENT_GEN_SEL_2 is still > referenced by rockchip_pcie_init_port(): You are correct, thanks for catching it. > > if (rockchip->link_gen == 2) > rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, > PCIE_CLIENT_CONFIG); > > This reference is removed by the next patch in the series but not sure > if we want to do it here instead. > > > #define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) > > #define PCIE_CLIENT_INT_IN_ASSERT HWORD_SET_BIT(0x0002) > > #define PCIE_CLIENT_INT_IN_DEASSERT HWORD_CLR_BIT(0x0002) > > @@ -197,8 +196,6 @@ > > (((x) & PCIE_CORE_PL_CONF_LS_MASK) == PCIE_CORE_PL_CONF_LS_READY) > > #define PCIE_LINK_UP(x) \ > > (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) > > -#define PCIE_LINK_IS_GEN2(x) \ > > - (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) > > Same for this, references elsewhere tho. > Thanks for pointing this out. I'll do better for v5. Geraldo Nascimento > > > > #define RC_REGION_0_ADDR_TRANS_H 0x00000000 > > #define RC_REGION_0_ADDR_TRANS_L 0x00000000