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From: Mark Rutland <mark.rutland@arm.com>
To: Ryan Roberts <ryan.roberts@arm.com>
Cc: Will Deacon <will@kernel.org>, Ard Biesheuvel <ardb@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Oliver Upton <oliver.upton@linux.dev>,
	Marc Zyngier <maz@kernel.org>, Dev Jain <dev.jain@arm.com>,
	Linu Cherian <Linu.Cherian@arm.com>,
	Jonathan Cameron <jonathan.cameron@huawei.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 13/13] arm64: mm: Provide level hint for flush_tlb_page()
Date: Mon, 2 Mar 2026 17:56:00 +0000	[thread overview]
Message-ID: <aaXPMPVoAWrK7PUR@J2N7QTR9R3> (raw)
In-Reply-To: <dca206e8-b430-4c02-aa4b-29216e3f31c6@arm.com>

On Mon, Mar 02, 2026 at 05:39:51PM +0000, Ryan Roberts wrote:
> On 02/03/2026 14:42, Mark Rutland wrote:
> > On Mon, Mar 02, 2026 at 01:56:00PM +0000, Ryan Roberts wrote:
> >> Previously tlb invalidations issued by __flush_tlb_page() did not
> >> contain a level hint. But the function is clearly only ever targeting
> >> level 3 tlb entries and its documentation agrees:
> >>
> >>   | this operation only invalidates a single, last-level page-table
> >>   | entry and therefore does not affect any walk-caches
> > 
> > FWIW, I'd have read "last-level" as synonymous with "leaf" (i.e. a Page
> > or Block entry, which is the last level of walk) rather than level 3
> > specifically. The architecture uses the term to match the former (e.g.
> > in the description of TLBI VALE1IS).
> 
> Hmm yeah, now that I'm re-reading, I agree that quoted documentation doesn't say
> anything about it being level 3 specific.
> 
> But actually that was arm64-specific documentation for flush_tlb_page(), which
> is a core-mm function. The generic docs at Documentation/core-api/cachetlb.rst
> make it clear that it's intended only for PTE invalidations, I think:
> 
>   | 4) ``void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)``
>   |
>   |        This time we need to remove the PAGE_SIZE sized translation
>   |        from the TLB. ...

Ah! I agree that's stronger and clearer.

> > If we're tightening up __flush_tlb_page(), I think it'd be worth either
> > updating the comment to explicitly note that this only applies to level
> > 3 entries, OR update the comment+name to say it applies to leaf entries,
> > and have it take a level parameter.
> 
> I'll fix the arm64-specific docs to align with the generic docs and replace
> "last-level" with "level 3" if that works for you.

Yep, saying "level 3" definitely works for me -- I just want this to be
explicit either way to minimize risk of confusion.

[...]

> >> However, it turns out that the function was actually being used to
> >> invalidate a level 2 mapping via flush_tlb_fix_spurious_fault_pmd(). 
> >> The bug was benign because the level hint was not set so the HW would
> >> still invalidate the PMD mapping, and also because the TLBF_NONOTIFY
> >> flag was set, the bounds of the mapping were never used for anything
> >> else.
> > 
> > I suspect (as above) that the current usage was intentional, legitimate
> > usage, just poorly documented.
> 
> Before this series flush_tlb_fix_spurious_fault_pmd() was implemented using
> local_flush_tlb_page_nonotify() which never even gives an option to set the TTL
> hint, so I agree.
> 
> But I don't think flush_tlb_fix_spurious_fault_pmd() should be calling any tlb
> flush api that has "page" in the name since that implies PTE, not PMD.
> 
> I think what I have done is an improvement; but I'm happy to soften/correct this
> description in the next version.

I think if you include the quote from the core API documentation above,
the rest is is good as is, and doesn't need to be softened.

> >> Now that we have the new and improved range-invalidation API, it is
> >> trival to fix flush_tlb_fix_spurious_fault_pmd() to explicitly flush the
> >> whole range (locally, without notification and last level only). So
> >> let's do that, and then update __flush_tlb_page() to hint level 3.
> > 
> > Do we never use __flush_tlb_page() to manipulate a level 1 block
> > mapping? I'd have expected we did the same lazy invalidation for
> > permission relazation there, but if that's not the case, then this seems
> > fine in principle.
> 
> No, there is no flush_tlb_fix_spurious_fault_pud().
> (flush_tlb_fix_spurious_fault_pmd() was only added last cycle).

Thanks for confirming; I just wasn't sure whether that didn't exist or
whether it had been possibly missed.

[...]

> >> -#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp)	\
> >> -	__flush_tlb_page(vma, address, TLBF_NOBROADCAST | TLBF_NONOTIFY)
> >> +#define flush_tlb_fix_spurious_fault_pmd(vma, address, pmdp)			\
> >> +	__flush_tlb_range(vma, address, address + PMD_SIZE, PMD_SIZE, 2,	\
> >> +			  TLBF_NOBROADCAST | TLBF_NONOTIFY | TLBF_NOWALKCACHE)
> > 
> > Is there a reason to keep __flush_tlb_page(), rather than defining
> > flush_tlb_fix_spurious_fault() in terms of __flush_tlb_range() with all
> > the level 3 constants?
> 
> __flush_tlb_page() is called by __ptep_clear_flush_young() and
> __ptep_set_access_flags() (as well as by flush_tlb_page()). I could replace them
> all, but __flush_tlb_page() is a bit less verbose... I have no strong preference.

That's reason enough to keep it; thanks for confirming, and sorry for
the noise!

Mark.


  reply	other threads:[~2026-03-02 17:56 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-03-02 13:55 [PATCH v3 00/13] arm64: Refactor TLB invalidation API and implementation Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 01/13] arm64: mm: Re-implement the __tlbi_level macro as a C function Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 02/13] arm64: mm: Introduce a C wrapper for by-range TLB invalidation Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 03/13] arm64: mm: Implicitly invalidate user ASID based on TLBI operation Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 04/13] arm64: mm: Push __TLBI_VADDR() into __tlbi_level() Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 05/13] arm64: mm: Inline __TLBI_VADDR_RANGE() into __tlbi_range() Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 06/13] arm64: mm: Re-implement the __flush_tlb_range_op macro in C Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 07/13] arm64: mm: Simplify __TLBI_RANGE_NUM() macro Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 08/13] arm64: mm: Simplify __flush_tlb_range_limit_excess() Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 09/13] arm64: mm: Refactor flush_tlb_page() to use __tlbi_level_asid() Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 10/13] arm64: mm: Refactor __flush_tlb_range() to take flags Ryan Roberts
2026-03-02 13:55 ` [PATCH v3 11/13] arm64: mm: More flags for __flush_tlb_range() Ryan Roberts
2026-03-03  9:57   ` Jonathan Cameron
2026-03-03 13:54     ` Ryan Roberts
2026-03-03 17:34       ` Jonathan Cameron
2026-03-02 13:55 ` [PATCH v3 12/13] arm64: mm: Wrap flush_tlb_page() around __do_flush_tlb_range() Ryan Roberts
2026-03-03  9:59   ` Jonathan Cameron
2026-03-02 13:56 ` [PATCH v3 13/13] arm64: mm: Provide level hint for flush_tlb_page() Ryan Roberts
2026-03-02 14:42   ` Mark Rutland
2026-03-02 17:39     ` Ryan Roberts
2026-03-02 17:56       ` Mark Rutland [this message]
2026-03-13 19:43 ` [PATCH v3 00/13] arm64: Refactor TLB invalidation API and implementation Catalin Marinas

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