[PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board

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* [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board
@ 2026-02-05 10:01 Stefano Radaelli
  2026-02-05 10:01 ` [PATCH v2 1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards Stefano Radaelli
                   ` (5 more replies)
  0 siblings, 6 replies; 15+ messages in thread
From: Stefano Radaelli @ 2026-02-05 10:01 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel
  Cc: kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

This patch series adds support for the Variscite DART-MX91 system on
module and the Sonata carrier board.

The series includes:
- Device tree bindings documentation for both SOM and carrier board
- SOM device tree with on-module peripherals
- Sonata carrier board device tree with board-specific features

The implementation follows the standard SOM + carrier board pattern
where the SOM dtsi contains only peripherals mounted on the module,
while carrier-specific interfaces are enabled in the board dts.

Stefano Radaelli (3):
  dt-bindings: arm: fsl: add Variscite DART-MX91 Boards
  arm64: dts: freescale: Add support for Variscite DART-MX91
  arm64: dts: imx91-var-dart: Add support for Variscite Sonata board

 .../devicetree/bindings/arm/fsl.yaml          |   6 +
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx91-var-dart-sonata.dts   | 498 ++++++++++++++++++
 .../boot/dts/freescale/imx91-var-dart.dtsi    | 468 ++++++++++++++++
 4 files changed, 973 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
 create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi


base-commit: 18f7fcd5e69a04df57b563360b88be72471d6b62
-- 
2.47.3



^ permalink raw reply	[flat|nested] 15+ messages in thread

* [PATCH v2 1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards
  2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
@ 2026-02-05 10:01 ` Stefano Radaelli
  2026-02-05 10:01 ` [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91 Stefano Radaelli
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 15+ messages in thread
From: Stefano Radaelli @ 2026-02-05 10:01 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel
  Cc: kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli, Conor Dooley

From: Stefano Radaelli <stefano.r@variscite.com>

Add DT compatible strings for Variscite DART-MX91 SoM and Variscite
development carrier Board.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 336669e16d7a..4c200a67600e 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1524,6 +1524,12 @@ properties:
           - const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
           - const: fsl,imx93
 
+      - description: Variscite DART-MX91 based boards
+        items:
+          - const: variscite,var-dart-mx91-sonata # Variscite DART-MX91 on Sonata Development Board
+          - const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM
+          - const: fsl,imx91
+
       - description: Variscite VAR-SOM-MX93 based boards
         items:
           - const: variscite,var-som-mx93-symphony
-- 
2.47.3



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91
  2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
  2026-02-05 10:01 ` [PATCH v2 1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards Stefano Radaelli
@ 2026-02-05 10:01 ` Stefano Radaelli
  2026-02-05 15:13   ` Frank Li
  2026-02-05 10:01 ` [PATCH v2 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board Stefano Radaelli
                   ` (3 subsequent siblings)
  5 siblings, 1 reply; 15+ messages in thread
From: Stefano Radaelli @ 2026-02-05 10:01 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel
  Cc: kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

From: Stefano Radaelli <stefano.r@variscite.com>

Add device tree support for the Variscite DART-MX91 system on module.
This SOM is designed to be used with various carrier boards.

The module includes:
- NXP i.MX91 MPU processor
- Up to 2GB of LPDDR4 memory
- Up to 128GB of eMMC storage memory
- Integrated 10/100/1000 Mbps Ethernet Transceiver
- Codec audio WM8904
- WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth

Only SOM-specific peripherals are enabled by default. Carrier board
specific interfaces are left disabled to be enabled in the respective
carrier board device trees.

Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/

Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
 .../boot/dts/freescale/imx91-var-dart.dtsi    | 468 ++++++++++++++++++
 1 file changed, 468 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi

diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
new file mode 100644
index 000000000000..e87b7abd86bb
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Common dtsi for Variscite DART-MX91
+ *
+ * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/
+ *
+ * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/usb/pd.h>
+#include "imx91.dtsi"
+
+/ {
+	model = "Variscite DART-MX91 Module";
+	compatible = "variscite,var-dart-mx91", "fsl,imx91";
+
+	sound-wm8904 {
+		compatible = "simple-audio-card";
+		simple-audio-card,bitclock-master = <&codec_dai>;
+		simple-audio-card,format = "i2s";
+		simple-audio-card,frame-master = <&codec_dai>;
+		simple-audio-card,mclk-fs = <256>;
+		simple-audio-card,name = "wm8904-audio";
+		simple-audio-card,routing =
+			"Headphone Jack", "HPOUTL",
+			"Headphone Jack", "HPOUTR",
+			"IN2L", "Line In Jack",
+			"IN2R", "Line In Jack",
+			"IN1L", "Microphone Jack",
+			"IN1R", "Microphone Jack";
+		simple-audio-card,widgets =
+			"Microphone", "Microphone Jack",
+			"Headphone", "Headphone Jack",
+			"Line", "Line In Jack";
+
+		codec_dai: simple-audio-card,codec {
+			sound-dai = <&wm8904>;
+		};
+
+		simple-audio-card,cpu {
+			sound-dai = <&sai1>;
+		};
+	};
+
+	wifi_pwrseq: wifi-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		post-power-on-delay-ms = <100>;
+		power-off-delay-us = <10000>;
+		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
+			      <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
+	};
+};
+
+&eqos {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_eqos>;
+	pinctrl-1 = <&pinctrl_eqos_sleep>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy0>;
+	snps,clk-csr = <5>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		clock-frequency = <1000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@0 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <0>;
+			reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <15000>;
+			reset-deassert-us = <100000>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_YELLOW>;
+					function = LED_FUNCTION_LAN;
+					linux,default-trigger = "netdev";
+				};
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					linux,default-trigger = "netdev";
+				};
+			};
+		};
+	};
+};
+
+&lpi2c3 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "sleep", "gpio";
+	pinctrl-0 = <&pinctrl_lpi2c3>;
+	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
+	pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
+	scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	wm8904: audio-codec@1a {
+		compatible = "wlf,wm8904";
+		reg = <0x1a>;
+		#sound-dai-cells = <0>;
+		clocks = <&clk IMX93_CLK_SAI1_GATE>;
+		clock-names = "mclk";
+		AVDD-supply = <&buck5>;
+		CPVDD-supply = <&buck5>;
+		DBVDD-supply = <&buck4>;
+		DCVDD-supply = <&buck5>;
+		MICVDD-supply = <&buck5>;
+		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
+				    "soft", "music";
+		/*
+		 * Config registers per name, respectively:
+		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
+		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
+		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
+		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
+		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
+		 */
+		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
+				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
+				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
+				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
+		/* GPIO1 = DMIC_CLK, don't touch others */
+		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
+		/* DMIC is connected to IN1L */
+		wlf,in1l-as-dmicdat1;
+	};
+
+	pmic@25 {
+		compatible = "nxp,pca9451a";
+		reg = <0x25>;
+
+		regulators {
+			buck1: BUCK1 {
+				regulator-name = "BUCK1";
+				regulator-min-microvolt = <650000>;
+				regulator-max-microvolt = <2237500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck2: BUCK2 {
+				regulator-name = "BUCK2";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <2187500>;
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-ramp-delay = <3125>;
+			};
+
+			buck4: BUCK4{
+				regulator-name = "BUCK4";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck5: BUCK5{
+				regulator-name = "BUCK5";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			buck6: BUCK6 {
+				regulator-name = "BUCK6";
+				regulator-min-microvolt = <600000>;
+				regulator-max-microvolt = <3400000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo1: LDO1 {
+				regulator-name = "LDO1";
+				regulator-min-microvolt = <1600000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo4: LDO4 {
+				regulator-name = "LDO4";
+				regulator-min-microvolt = <800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			ldo5: LDO5 {
+				regulator-name = "LDO5";
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+		};
+	};
+};
+
+/* BT module */
+&lpuart5 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
+	uart-has-rtscts;
+	status = "okay";
+
+	bluetooth {
+		compatible = "nxp,88w8987-bt";
+	};
+};
+
+&sai1 {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_sai1>;
+	pinctrl-1 = <&pinctrl_sai1_sleep>;
+	assigned-clocks = <&clk IMX93_CLK_SAI1>;
+	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
+	assigned-clock-rates = <12288000>;
+	#sound-dai-cells = <0>;
+	fsl,sai-mclk-direction-output;
+	status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	bus-width = <8>;
+	non-removable;
+	status = "okay";
+};
+
+/* WiFi */
+&usdhc3 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
+	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
+	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
+	pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
+	mmc-pwrseq = <&wifi_pwrseq>;
+	keep-power-in-suspend;
+	bus-width = <4>;
+	non-removable;
+	wakeup-source;
+	status = "okay";
+};
+
+&wdog3 {
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_bt: btgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_MDIO__GPIO4_IO15				0x51e
+		>;
+	};
+
+	pinctrl_eqos: eqosgrp {
+		fsl,pins = <
+			MX91_PAD_ENET1_MDC__ENET1_MDC				0x57e
+			MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
+			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
+			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
+			MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
+			MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
+			MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC			0x5fe
+			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
+			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
+			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1			0x57e
+			MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
+			MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
+			MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
+			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
+			MX91_PAD_UART2_TXD__GPIO1_IO7				0x51e
+		>;
+	};
+
+	pinctrl_eqos_sleep: eqos-sleepgrp {
+		fsl,pins = <
+			MX91_PAD_ENET1_MDC__GPIO4_IO0				0x31e
+			MX91_PAD_ENET1_MDIO__GPIO4_IO1				0x31e
+			MX91_PAD_ENET1_RD0__GPIO4_IO10				0x31e
+			MX91_PAD_ENET1_RD1__GPIO4_IO11				0x31e
+			MX91_PAD_ENET1_RD2__GPIO4_IO12				0x31e
+			MX91_PAD_ENET1_RD3__GPIO4_IO13				0x31e
+			MX91_PAD_ENET1_RXC__GPIO4_IO9				0x31e
+			MX91_PAD_ENET1_RX_CTL__GPIO4_IO8			0x31e
+			MX91_PAD_ENET1_TD0__GPIO4_IO5				0x31e
+			MX91_PAD_ENET1_TD1__GPIO4_IO4				0x31e
+			MX91_PAD_ENET1_TD2__GPIO4_IO3				0x31e
+			MX91_PAD_ENET1_TD3__GPIO4_IO2				0x31e
+			MX91_PAD_ENET1_TXC__GPIO4_IO7				0x31e
+			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6			0x31e
+		>;
+	};
+
+	pinctrl_lpi2c3: lpi2c3grp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO28__LPI2C3_SDA				0x40000b9e
+			MX91_PAD_GPIO_IO29__LPI2C3_SCL				0x40000b9e
+		>;
+	};
+
+	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO28__GPIO2_IO28				0x40000b9e
+			MX91_PAD_GPIO_IO29__GPIO2_IO29				0x40000b9e
+		>;
+	};
+
+	pinctrl_sai1: sai1grp {
+		fsl,pins = <
+			MX91_PAD_SAI1_TXC__SAI1_TX_BCLK				0x31e
+			MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC			0x31e
+			MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0			0x31e
+			MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0			0x31e
+			MX91_PAD_I2C2_SDA__SAI1_RX_BCLK				0x31e
+			MX91_PAD_I2C2_SCL__SAI1_RX_SYNC				0x31e
+			MX91_PAD_UART2_RXD__SAI1_MCLK				0x31e
+		>;
+	};
+
+	pinctrl_sai1_sleep: sai1-sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SAI1_TXC__GPIO1_IO12				0x31e
+			MX91_PAD_SAI1_TXFS__GPIO1_IO11				0x31e
+			MX91_PAD_SAI1_TXD0__GPIO1_IO13				0x31e
+			MX91_PAD_SAI1_RXD0__GPIO1_IO14				0x31e
+			MX91_PAD_UART2_RXD__GPIO1_IO6				0x31e
+			MX91_PAD_I2C2_SDA__GPIO1_IO3				0x31e
+			MX91_PAD_I2C2_SCL__GPIO1_IO2				0x31e
+		>;
+	};
+
+	pinctrl_uart5: uart5grp {
+		fsl,pins = <
+			MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX			0x31e
+			MX91_PAD_DAP_TDI__LPUART5_RX				0x31e
+			MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B			0x31e
+			MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B			0x31e
+		>;
+	};
+
+	pinctrl_usdhc1: usdhc1grp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK				0x1582
+			MX91_PAD_SD1_CMD__USDHC1_CMD				0x1382
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x1382
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x1382
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x1382
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x1382
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x1382
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x1382
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x1382
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x1382
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x1582
+		>;
+	};
+
+	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK				0x158e
+			MX91_PAD_SD1_CMD__USDHC1_CMD				0x138e
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x138e
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x138e
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x138e
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x138e
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x138e
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x138e
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x138e
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x138e
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x158e
+		>;
+	};
+
+	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD1_CLK__USDHC1_CLK				0x15fe
+			MX91_PAD_SD1_CMD__USDHC1_CMD				0x13fe
+			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe
+			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe
+			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe
+			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe
+			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe
+			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe
+			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe
+			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe
+			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK				0x1582
+			MX91_PAD_SD3_CMD__USDHC3_CMD				0x1382
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x1382
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x1382
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x1382
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x1382
+		>;
+	};
+
+	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK				0x158e
+			MX91_PAD_SD3_CMD__USDHC3_CMD				0x138e
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x138e
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x138e
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x138e
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x138e
+		>;
+	};
+
+	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__USDHC3_CLK				0x15fe
+			MX91_PAD_SD3_CMD__USDHC3_CMD				0x13fe
+			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x13fe
+			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x13fe
+			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x13fe
+			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x13fe
+		>;
+	};
+
+	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD3_CLK__GPIO3_IO20				0x31e
+			MX91_PAD_SD3_CMD__GPIO3_IO21				0x31e
+			MX91_PAD_SD3_DATA0__GPIO3_IO22				0x31e
+			MX91_PAD_SD3_DATA1__GPIO3_IO23				0x31e
+			MX91_PAD_SD3_DATA2__GPIO3_IO24				0x31e
+			MX91_PAD_SD3_DATA3__GPIO3_IO25				0x31e
+		>;
+	};
+
+	pinctrl_usdhc3_wlan: usdhc3wlangrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_MDC__GPIO4_IO14				0x51e
+			MX91_PAD_SD2_RESET_B__GPIO3_IO7				0x51e
+		>;
+	};
+};
-- 
2.47.3



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* [PATCH v2 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board
  2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
  2026-02-05 10:01 ` [PATCH v2 1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards Stefano Radaelli
  2026-02-05 10:01 ` [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91 Stefano Radaelli
@ 2026-02-05 10:01 ` Stefano Radaelli
  2026-02-05 15:12   ` Frank Li
  2026-02-05 10:14 ` [PATCH v2 0/3] Add support for Variscite DART-MX91 and " Daniel Baluta
                   ` (2 subsequent siblings)
  5 siblings, 1 reply; 15+ messages in thread
From: Stefano Radaelli @ 2026-02-05 10:01 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel
  Cc: kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

From: Stefano Radaelli <stefano.r@variscite.com>

Add device tree support for the Variscite Sonata carrier board with
the DART-MX91 system on module.

The Sonata board includes
- uSD Card support
- USB ports and OTG
- Additional Gigabit Ethernet interface
- Uart interfaces
- GPIO Expanders
- RTC module
- TPM module

Link: https://variscite.com/carrier-boards/sonata-board/
Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
---
 arch/arm64/boot/dts/freescale/Makefile        |   1 +
 .../dts/freescale/imx91-var-dart-sonata.dts   | 498 ++++++++++++++++++
 2 files changed, 499 insertions(+)
 create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts

diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index f30d3fd724d0..839d98bdd2a1 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -370,6 +370,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb
 dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
 
 imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
new file mode 100644
index 000000000000..b3c74feaf644
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Variscite Sonata carrier board for DART-MX91
+ *
+ * Link: https://variscite.com/carrier-boards/sonata-board/
+ *
+ * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
+ *
+ */
+
+/dts-v1/;
+
+#include "imx91-var-dart.dtsi"
+
+/ {
+	model = "Variscite DART-MX91 on Sonata-Board";
+	compatible = "variscite,var-dart-mx91-sonata",
+		     "variscite,var-dart-mx91",
+		     "fsl,imx91";
+
+	aliases {
+		ethernet0 = &eqos;
+		ethernet1 = &fec;
+		gpio0 = &gpio1;
+		gpio1 = &gpio2;
+		gpio2 = &gpio3;
+		i2c0 = &lpi2c1;
+		i2c1 = &lpi2c2;
+		i2c2 = &lpi2c3;
+		mmc0 = &usdhc1;
+		mmc1 = &usdhc2;
+		serial0 = &lpuart1;
+		serial1 = &lpuart2;
+		serial2 = &lpuart3;
+		serial3 = &lpuart4;
+		serial4 = &lpuart5;
+		serial5 = &lpuart6;
+	};
+
+	chosen {
+		stdout-path = &lpuart1;
+	};
+
+	gpio-keys {
+		compatible = "gpio-keys";
+
+		button-home {
+			label = "Home";
+			linux,code = <KEY_HOME>;
+			gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-up {
+			label = "Up";
+			linux,code = <KEY_UP>;
+			gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-down {
+			label = "Down";
+			linux,code = <KEY_DOWN>;
+			gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+
+		button-back {
+			label = "Back";
+			linux,code = <KEY_BACK>;
+			gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
+			wakeup-source;
+		};
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		led-emmc {
+			label = "eMMC";
+			gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "mmc0";
+		};
+	};
+
+	reg_vref_1v8: regulator-adc-vref {
+		compatible = "regulator-fixed";
+		regulator-name = "vref_1v8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+	};
+
+	reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
+		regulator-name = "VDD_SD2_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		off-on-delay-us = <20000>;
+	};
+
+	reserved-memory {
+		ranges;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			alloc-ranges = <0 0x80000000 0 0x40000000>;
+			reusable;
+			size = <0 0x10000000>;
+			linux,cma-default;
+		};
+	};
+};
+
+&adc1 {
+	vref-supply = <&reg_vref_1v8>;
+	status = "okay";
+};
+
+/* Use external instead of internal RTC */
+&bbnsm_rtc {
+	status = "disabled";
+};
+
+&eqos {
+	mdio {
+		ethphy1: ethernet-phy@1 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <1>;
+			reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
+			reset-assert-us = <15000>;
+			reset-deassert-us = <100000>;
+
+			leds {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				led@0 {
+					reg = <0>;
+					color = <LED_COLOR_ID_YELLOW>;
+					function = LED_FUNCTION_LAN;
+					linux,default-trigger = "netdev";
+				};
+
+				led@1 {
+					reg = <1>;
+					color = <LED_COLOR_ID_GREEN>;
+					function = LED_FUNCTION_LAN;
+					linux,default-trigger = "netdev";
+				};
+			};
+		};
+	};
+};
+
+&fec {
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&pinctrl_fec>;
+	pinctrl-1 = <&pinctrl_fec_sleep>;
+	/*
+	 * The required RGMII TX and RX 2ns delays are implemented directly
+	 * in hardware via passive delay elements on the SOM PCB.
+	 * No delay configuration is needed in software via PHY driver.
+	 */
+	phy-mode = "rgmii";
+	phy-handle = <&ethphy1>;
+	status = "okay";
+};
+
+&flexcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_flexcan1>;
+	status = "okay";
+};
+
+&lpi2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default", "sleep", "gpio";
+	pinctrl-0 = <&pinctrl_lpi2c1>;
+	pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
+	pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
+	scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
+	status = "okay";
+
+	pca6408_1: gpio@20 {
+		compatible = "nxp,pcal6408";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pca6408_2: gpio@21 {
+		compatible = "nxp,pcal6408";
+		reg = <0x21>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pca9534: gpio@22 {
+		compatible = "nxp,pca9534";
+		reg = <0x22>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-parent = <&gpio1>;
+		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	st33ktpm2xi2c: tpm@2e {
+		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
+		reg = <0x2e>;
+	};
+
+	/* Capacitive touch controller */
+	ft5x06_ts: touchscreen@38 {
+		compatible = "edt,edt-ft5206";
+		reg = <0x38>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_captouch>;
+		reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
+		interrupt-parent = <&gpio3>;
+		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
+		touchscreen-size-x = <800>;
+		touchscreen-size-y = <480>;
+		touchscreen-inverted-x;
+		touchscreen-inverted-y;
+		wakeup-source;
+	};
+
+	/* USB Type-C Controller */
+	typec@3d {
+		compatible = "nxp,ptn5150";
+		reg = <0x3d>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_extcon>;
+		interrupt-parent = <&gpio4>;
+		interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
+
+		port {
+			typec1_dr_sw: endpoint {
+				remote-endpoint = <&usb1_drd_sw>;
+			};
+		};
+	};
+
+	rtc@68 {
+		compatible = "dallas,ds1337";
+		reg = <0x68>;
+	};
+};
+
+/* Console (J10) */
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+/* Header (J12.4, J12.6) */
+&lpuart6 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart6>;
+	status = "okay";
+};
+
+&usbotg1 {
+	dr_mode = "otg";
+	hnp-disable;
+	srp-disable;
+	adp-disable;
+	usb-role-switch;
+	disable-over-current;
+	samsung,picophy-pre-emp-curr-control = <3>;
+	samsung,picophy-dc-vol-level-adjust = <7>;
+	status = "okay";
+
+	port {
+		usb1_drd_sw: endpoint {
+			remote-endpoint = <&typec1_dr_sw>;
+		};
+	};
+};
+
+&usbotg2 {
+	disable-over-current;
+	dr_mode = "host";
+	status = "okay";
+};
+
+/* SD */
+&usdhc2 {
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&reg_usdhc2_vmmc>;
+	bus-width = <4>;
+	no-sdio;
+	no-mmc;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog>;
+
+	pinctrl_hog: hoggrp {
+		fsl,pins = <
+			/* GPIO Expanders shared IRQ */
+			MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10            0x31e
+		>;
+	};
+
+	pinctrl_captouch: captouchgrp {
+		fsl,pins = <
+			MX91_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
+		>;
+	};
+
+	pinctrl_extcon: extcongrp {
+		fsl,pins = <
+			MX91_PAD_CCM_CLKO4__GPIO4_IO29			0x31e
+		>;
+	};
+
+	pinctrl_fec: fecgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0             0x57e
+			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1             0x57e
+			MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2             0x57e
+			MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3             0x37e
+			MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC             0x5fe
+			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL       0x57e
+			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0             0x57e
+			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1             0x57e
+			MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2             0x57e
+			MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3             0x57e
+			MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC             0x5fe
+			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL       0x57e
+		>;
+	};
+
+	pinctrl_fec_sleep: fecsleepgrp {
+		fsl,pins = <
+			MX91_PAD_ENET2_RD0__GPIO4_IO24                  0x51e
+			MX91_PAD_ENET2_RD1__GPIO4_IO25                  0x51e
+			MX91_PAD_ENET2_RD2__GPIO4_IO26                  0x51e
+			MX91_PAD_ENET2_RD3__GPIO4_IO27                  0x31e
+			MX91_PAD_ENET2_RXC__GPIO4_IO23                  0x51e
+			MX91_PAD_ENET2_RX_CTL__GPIO4_IO22               0x51e
+			MX91_PAD_ENET2_TD0__GPIO4_IO19                  0x51e
+			MX91_PAD_ENET2_TD1__GPIO4_IO18                  0x51e
+			MX91_PAD_ENET2_TD2__GPIO4_IO17                  0x51e
+			MX91_PAD_ENET2_TD3__GPIO4_IO16                  0x51e
+			MX91_PAD_ENET2_TXC__GPIO4_IO21                  0x51e
+			MX91_PAD_ENET2_TX_CTL__GPIO4_IO20               0x51e
+		>;
+	};
+
+	pinctrl_flexcan1: flexcan1grp {
+		fsl,pins = <
+			MX91_PAD_PDM_CLK__CAN1_TX			0x139e
+			MX91_PAD_PDM_BIT_STREAM0__CAN1_RX		0x139e
+		>;
+	};
+
+	pinctrl_lpi2c1: lpi2c1grp {
+		fsl,pins = <
+			MX91_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
+			MX91_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
+		>;
+	};
+
+	pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp {
+		fsl,pins = <
+			MX91_PAD_I2C1_SCL__GPIO1_IO0			0x31e
+			MX91_PAD_I2C1_SDA__GPIO1_IO1			0x31e
+		>;
+	};
+
+	pinctrl_lpi2c7: lpi2c7grp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO07__LPI2C7_SCL			0x40000b9e
+			MX91_PAD_GPIO_IO06__LPI2C7_SDA			0x40000b9e
+		>;
+	};
+
+	pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO07__GPIO2_IO7			0x31e
+			MX91_PAD_GPIO_IO06__GPIO2_IO6			0x31e
+		>;
+	};
+
+	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
+		fsl,pins = <
+			MX91_PAD_CCM_CLKO3__GPIO4_IO28			0x31e
+		>;
+	};
+
+	pinctrl_rtc: rtcgrp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO02__GPIO2_IO2			0x31e
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX91_PAD_UART1_RXD__LPUART1_RX			0x31e
+			MX91_PAD_UART1_TXD__LPUART1_TX			0x31e
+		>;
+	};
+
+	pinctrl_uart6: uart6grp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO05__LPUART6_RX			0x31e
+			MX91_PAD_GPIO_IO04__LPUART6_TX			0x31e
+		>;
+	};
+
+	pinctrl_uart7: uart7grp {
+		fsl,pins = <
+			MX91_PAD_GPIO_IO09__LPUART7_RX			0x31e
+			MX91_PAD_GPIO_IO08__LPUART7_TX			0x31e
+		>;
+	};
+
+	pinctrl_usdhc2: usdhc2grp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK			0x1582
+			MX91_PAD_SD2_CMD__USDHC2_CMD			0x1382
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x1382
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x1382
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x1382
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x1382
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK			0x158e
+			MX91_PAD_SD2_CMD__USDHC2_CMD			0x138e
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__USDHC2_CLK			0x15fe
+			MX91_PAD_SD2_CMD__USDHC2_CMD			0x13fe
+			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe
+			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe
+			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe
+			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe
+			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_sleep: usdhc2sleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CLK__GPIO3_IO1			0x51e
+			MX91_PAD_SD2_CMD__GPIO3_IO2			0x51e
+			MX91_PAD_SD2_DATA0__GPIO3_IO3			0x51e
+			MX91_PAD_SD2_DATA1__GPIO3_IO4			0x51e
+			MX91_PAD_SD2_DATA2__GPIO3_IO5			0x51e
+			MX91_PAD_SD2_DATA3__GPIO3_IO6			0x51e
+			MX91_PAD_SD2_VSELECT__GPIO3_IO19		0x51e
+		>;
+	};
+
+	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CD_B__GPIO3_IO0			0x31e
+		>;
+	};
+
+	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
+		fsl,pins = <
+			MX91_PAD_SD2_CD_B__GPIO3_IO0			0x51e
+		>;
+	};
+};
-- 
2.47.3



^ permalink raw reply related	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board
  2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
                   ` (2 preceding siblings ...)
  2026-02-05 10:01 ` [PATCH v2 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board Stefano Radaelli
@ 2026-02-05 10:14 ` Daniel Baluta
  2026-02-05 15:09 ` Frank Li
  2026-03-02 16:24 ` (subset) " Frank Li
  5 siblings, 0 replies; 15+ messages in thread
From: Daniel Baluta @ 2026-02-05 10:14 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 5, 2026 at 12:03 PM Stefano Radaelli
<stefano.radaelli21@gmail.com> wrote:
>
> This patch series adds support for the Variscite DART-MX91 system on
> module and the Sonata carrier board.
>
> The series includes:
> - Device tree bindings documentation for both SOM and carrier board
> - SOM device tree with on-module peripherals
> - Sonata carrier board device tree with board-specific features
>
> The implementation follows the standard SOM + carrier board pattern
> where the SOM dtsi contains only peripherals mounted on the module,
> while carrier-specific interfaces are enabled in the board dts.
>
> Stefano Radaelli (3):
>   dt-bindings: arm: fsl: add Variscite DART-MX91 Boards
>   arm64: dts: freescale: Add support for Variscite DART-MX91
>   arm64: dts: imx91-var-dart: Add support for Variscite Sonata board
>
>  .../devicetree/bindings/arm/fsl.yaml          |   6 +
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  .../dts/freescale/imx91-var-dart-sonata.dts   | 498 ++++++++++++++++++
>  .../boot/dts/freescale/imx91-var-dart.dtsi    | 468 ++++++++++++++++
>  4 files changed, 973 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi

LGTM for entire series:

Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>

For next series please add a changelog for each new version added so
that reviewers
can easily follow what have changed since previous version.


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board
  2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
                   ` (3 preceding siblings ...)
  2026-02-05 10:14 ` [PATCH v2 0/3] Add support for Variscite DART-MX91 and " Daniel Baluta
@ 2026-02-05 15:09 ` Frank Li
  2026-02-05 15:18   ` Stefano Radaelli
  2026-03-02 16:24 ` (subset) " Frank Li
  5 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2026-02-05 15:09 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 05, 2026 at 11:01:22AM +0100, Stefano Radaelli wrote:
> This patch series adds support for the Variscite DART-MX91 system on
> module and the Sonata carrier board.
>
> The series includes:
> - Device tree bindings documentation for both SOM and carrier board
> - SOM device tree with on-module peripherals
> - Sonata carrier board device tree with board-specific features
>
> The implementation follows the standard SOM + carrier board pattern
> where the SOM dtsi contains only peripherals mounted on the module,
> while carrier-specific interfaces are enabled in the board dts.
>
> Stefano Radaelli (3):
>   dt-bindings: arm: fsl: add Variscite DART-MX91 Boards
>   arm64: dts: freescale: Add support for Variscite DART-MX91
>   arm64: dts: imx91-var-dart: Add support for Variscite Sonata board
>
>  .../devicetree/bindings/arm/fsl.yaml          |   6 +
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  .../dts/freescale/imx91-var-dart-sonata.dts   | 498 ++++++++++++++++++
>  .../boot/dts/freescale/imx91-var-dart.dtsi    | 468 ++++++++++++++++
>  4 files changed, 973 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
>  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi

where your v2 change log?

Frank
>
>
> base-commit: 18f7fcd5e69a04df57b563360b88be72471d6b62
> --
> 2.47.3
>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board
  2026-02-05 10:01 ` [PATCH v2 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board Stefano Radaelli
@ 2026-02-05 15:12   ` Frank Li
  0 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2026-02-05 15:12 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 05, 2026 at 11:01:25AM +0100, Stefano Radaelli wrote:
> From: Stefano Radaelli <stefano.r@variscite.com>
>
> Add device tree support for the Variscite Sonata carrier board with
> the DART-MX91 system on module.
>
> The Sonata board includes
> - uSD Card support
> - USB ports and OTG
> - Additional Gigabit Ethernet interface
> - Uart interfaces
> - GPIO Expanders
> - RTC module
> - TPM module
>
> Link: https://variscite.com/carrier-boards/sonata-board/
> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  arch/arm64/boot/dts/freescale/Makefile        |   1 +
>  .../dts/freescale/imx91-var-dart-sonata.dts   | 498 ++++++++++++++++++
>  2 files changed, 499 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index f30d3fd724d0..839d98bdd2a1 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -370,6 +370,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx91-11x11-evk.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx91-phyboard-segin.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx91-tqma9131-mba91xxca.dtb
> +dtb-$(CONFIG_ARCH_MXC) += imx91-var-dart-sonata.dtb
>  dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
>
>  imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
> diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
> new file mode 100644
> index 000000000000..b3c74feaf644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart-sonata.dts
> @@ -0,0 +1,498 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Variscite Sonata carrier board for DART-MX91
> + *
> + * Link: https://variscite.com/carrier-boards/sonata-board/
> + *
> + * Copyright (C) 2025 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include "imx91-var-dart.dtsi"
> +
> +/ {
> +	model = "Variscite DART-MX91 on Sonata-Board";
> +	compatible = "variscite,var-dart-mx91-sonata",
> +		     "variscite,var-dart-mx91",
> +		     "fsl,imx91";
> +
> +	aliases {
> +		ethernet0 = &eqos;
> +		ethernet1 = &fec;
> +		gpio0 = &gpio1;
> +		gpio1 = &gpio2;
> +		gpio2 = &gpio3;
> +		i2c0 = &lpi2c1;
> +		i2c1 = &lpi2c2;
> +		i2c2 = &lpi2c3;
> +		mmc0 = &usdhc1;
> +		mmc1 = &usdhc2;
> +		serial0 = &lpuart1;
> +		serial1 = &lpuart2;
> +		serial2 = &lpuart3;
> +		serial3 = &lpuart4;
> +		serial4 = &lpuart5;
> +		serial5 = &lpuart6;
> +	};
> +
> +	chosen {
> +		stdout-path = &lpuart1;
> +	};
> +
> +	gpio-keys {
> +		compatible = "gpio-keys";
> +
> +		button-home {
> +			label = "Home";
> +			linux,code = <KEY_HOME>;
> +			gpios = <&pca6408_1 4 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-up {
> +			label = "Up";
> +			linux,code = <KEY_UP>;
> +			gpios = <&pca6408_1 5 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-down {
> +			label = "Down";
> +			linux,code = <KEY_DOWN>;
> +			gpios = <&pca6408_1 6 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +
> +		button-back {
> +			label = "Back";
> +			linux,code = <KEY_BACK>;
> +			gpios = <&pca6408_1 7 GPIO_ACTIVE_LOW>;
> +			wakeup-source;
> +		};
> +	};
> +
> +	gpio-leds {
> +		compatible = "gpio-leds";
> +
> +		led-emmc {
> +			label = "eMMC";
> +			gpios = <&pca6408_2 7 GPIO_ACTIVE_HIGH>;
> +			linux,default-trigger = "mmc0";
> +		};
> +	};
> +
> +	reg_vref_1v8: regulator-adc-vref {
> +		compatible = "regulator-fixed";
> +		regulator-name = "vref_1v8";
> +		regulator-min-microvolt = <1800000>;
> +		regulator-max-microvolt = <1800000>;
> +	};
> +
> +	reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
> +		compatible = "regulator-fixed";
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
> +		regulator-name = "VDD_SD2_3V3";
> +		regulator-min-microvolt = <3300000>;
> +		regulator-max-microvolt = <3300000>;
> +		gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
> +		enable-active-high;
> +		off-on-delay-us = <20000>;
> +	};
> +
> +	reserved-memory {
> +		ranges;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +
> +		linux,cma {
> +			compatible = "shared-dma-pool";
> +			alloc-ranges = <0 0x80000000 0 0x40000000>;
> +			reusable;
> +			size = <0 0x10000000>;
> +			linux,cma-default;
> +		};
> +	};
> +};
> +
> +&adc1 {
> +	vref-supply = <&reg_vref_1v8>;
> +	status = "okay";
> +};
> +
> +/* Use external instead of internal RTC */
> +&bbnsm_rtc {
> +	status = "disabled";
> +};
> +
> +&eqos {
> +	mdio {
> +		ethphy1: ethernet-phy@1 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <1>;
> +			reset-gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <15000>;
> +			reset-deassert-us = <100000>;
> +
> +			leds {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				led@0 {
> +					reg = <0>;
> +					color = <LED_COLOR_ID_YELLOW>;
> +					function = LED_FUNCTION_LAN;
> +					linux,default-trigger = "netdev";
> +				};
> +
> +				led@1 {
> +					reg = <1>;
> +					color = <LED_COLOR_ID_GREEN>;
> +					function = LED_FUNCTION_LAN;
> +					linux,default-trigger = "netdev";
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&fec {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&pinctrl_fec>;
> +	pinctrl-1 = <&pinctrl_fec_sleep>;
> +	/*
> +	 * The required RGMII TX and RX 2ns delays are implemented directly
> +	 * in hardware via passive delay elements on the SOM PCB.
> +	 * No delay configuration is needed in software via PHY driver.
> +	 */
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy1>;
> +	status = "okay";
> +};
> +
> +&flexcan1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_flexcan1>;
> +	status = "okay";
> +};
> +
> +&lpi2c1 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default", "sleep", "gpio";
> +	pinctrl-0 = <&pinctrl_lpi2c1>;
> +	pinctrl-1 = <&pinctrl_lpi2c1_gpio>;
> +	pinctrl-2 = <&pinctrl_lpi2c1_gpio>;
> +	scl-gpios = <&gpio1 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +
> +	pca6408_1: gpio@20 {
> +		compatible = "nxp,pcal6408";
> +		reg = <0x20>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	pca6408_2: gpio@21 {
> +		compatible = "nxp,pcal6408";
> +		reg = <0x21>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	pca9534: gpio@22 {
> +		compatible = "nxp,pca9534";
> +		reg = <0x22>;
> +		gpio-controller;
> +		#gpio-cells = <2>;
> +		interrupt-parent = <&gpio1>;
> +		interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
> +	};
> +
> +	st33ktpm2xi2c: tpm@2e {
> +		compatible = "st,st33ktpm2xi2c", "tcg,tpm-tis-i2c";
> +		reg = <0x2e>;
> +	};
> +
> +	/* Capacitive touch controller */
> +	ft5x06_ts: touchscreen@38 {
> +		compatible = "edt,edt-ft5206";
> +		reg = <0x38>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_captouch>;
> +		reset-gpios = <&pca6408_2 4 GPIO_ACTIVE_LOW>;
> +		interrupt-parent = <&gpio3>;
> +		interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
> +		touchscreen-size-x = <800>;
> +		touchscreen-size-y = <480>;
> +		touchscreen-inverted-x;
> +		touchscreen-inverted-y;
> +		wakeup-source;
> +	};
> +
> +	/* USB Type-C Controller */
> +	typec@3d {
> +		compatible = "nxp,ptn5150";
> +		reg = <0x3d>;
> +		pinctrl-names = "default";
> +		pinctrl-0 = <&pinctrl_extcon>;
> +		interrupt-parent = <&gpio4>;
> +		interrupts = <29 IRQ_TYPE_LEVEL_HIGH>;
> +
> +		port {
> +			typec1_dr_sw: endpoint {
> +				remote-endpoint = <&usb1_drd_sw>;
> +			};
> +		};
> +	};
> +
> +	rtc@68 {
> +		compatible = "dallas,ds1337";
> +		reg = <0x68>;
> +	};
> +};
> +
> +/* Console (J10) */
> +&lpuart1 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart1>;
> +	status = "okay";
> +};
> +
> +/* Header (J12.4, J12.6) */
> +&lpuart6 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart6>;
> +	status = "okay";
> +};
> +
> +&usbotg1 {
> +	dr_mode = "otg";
> +	hnp-disable;
> +	srp-disable;
> +	adp-disable;
> +	usb-role-switch;
> +	disable-over-current;
> +	samsung,picophy-pre-emp-curr-control = <3>;
> +	samsung,picophy-dc-vol-level-adjust = <7>;
> +	status = "okay";
> +
> +	port {
> +		usb1_drd_sw: endpoint {
> +			remote-endpoint = <&typec1_dr_sw>;
> +		};
> +	};
> +};
> +
> +&usbotg2 {
> +	disable-over-current;
> +	dr_mode = "host";
> +	status = "okay";
> +};
> +
> +/* SD */
> +&usdhc2 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> +	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
> +	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
> +	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
> +	vmmc-supply = <&reg_usdhc2_vmmc>;
> +	bus-width = <4>;
> +	no-sdio;
> +	no-mmc;
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hog>;
> +
> +	pinctrl_hog: hoggrp {
> +		fsl,pins = <
> +			/* GPIO Expanders shared IRQ */
> +			MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10            0x31e
> +		>;
> +	};
> +
> +	pinctrl_captouch: captouchgrp {
> +		fsl,pins = <
> +			MX91_PAD_CCM_CLKO2__GPIO3_IO27			0x31e
> +		>;
> +	};
> +
> +	pinctrl_extcon: extcongrp {
> +		fsl,pins = <
> +			MX91_PAD_CCM_CLKO4__GPIO4_IO29			0x31e
> +		>;
> +	};
> +
> +	pinctrl_fec: fecgrp {
> +		fsl,pins = <
> +			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0             0x57e
> +			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1             0x57e
> +			MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2             0x57e
> +			MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3             0x37e
> +			MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC             0x5fe
> +			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL       0x57e
> +			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0             0x57e
> +			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1             0x57e
> +			MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2             0x57e
> +			MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3             0x57e
> +			MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC             0x5fe
> +			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL       0x57e
> +		>;
> +	};
> +
> +	pinctrl_fec_sleep: fecsleepgrp {
> +		fsl,pins = <
> +			MX91_PAD_ENET2_RD0__GPIO4_IO24                  0x51e
> +			MX91_PAD_ENET2_RD1__GPIO4_IO25                  0x51e
> +			MX91_PAD_ENET2_RD2__GPIO4_IO26                  0x51e
> +			MX91_PAD_ENET2_RD3__GPIO4_IO27                  0x31e
> +			MX91_PAD_ENET2_RXC__GPIO4_IO23                  0x51e
> +			MX91_PAD_ENET2_RX_CTL__GPIO4_IO22               0x51e
> +			MX91_PAD_ENET2_TD0__GPIO4_IO19                  0x51e
> +			MX91_PAD_ENET2_TD1__GPIO4_IO18                  0x51e
> +			MX91_PAD_ENET2_TD2__GPIO4_IO17                  0x51e
> +			MX91_PAD_ENET2_TD3__GPIO4_IO16                  0x51e
> +			MX91_PAD_ENET2_TXC__GPIO4_IO21                  0x51e
> +			MX91_PAD_ENET2_TX_CTL__GPIO4_IO20               0x51e
> +		>;
> +	};
> +
> +	pinctrl_flexcan1: flexcan1grp {
> +		fsl,pins = <
> +			MX91_PAD_PDM_CLK__CAN1_TX			0x139e
> +			MX91_PAD_PDM_BIT_STREAM0__CAN1_RX		0x139e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c1: lpi2c1grp {
> +		fsl,pins = <
> +			MX91_PAD_I2C1_SCL__LPI2C1_SCL			0x40000b9e
> +			MX91_PAD_I2C1_SDA__LPI2C1_SDA			0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c1_gpio: lpi2c1-gpiogrp {
> +		fsl,pins = <
> +			MX91_PAD_I2C1_SCL__GPIO1_IO0			0x31e
> +			MX91_PAD_I2C1_SDA__GPIO1_IO1			0x31e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c7: lpi2c7grp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO07__LPI2C7_SCL			0x40000b9e
> +			MX91_PAD_GPIO_IO06__LPI2C7_SDA			0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c7_gpio: lpi2c7-gpiogrp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO07__GPIO2_IO7			0x31e
> +			MX91_PAD_GPIO_IO06__GPIO2_IO6			0x31e
> +		>;
> +	};
> +
> +	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
> +		fsl,pins = <
> +			MX91_PAD_CCM_CLKO3__GPIO4_IO28			0x31e
> +		>;
> +	};
> +
> +	pinctrl_rtc: rtcgrp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO02__GPIO2_IO2			0x31e
> +		>;
> +	};
> +
> +	pinctrl_uart1: uart1grp {
> +		fsl,pins = <
> +			MX91_PAD_UART1_RXD__LPUART1_RX			0x31e
> +			MX91_PAD_UART1_TXD__LPUART1_TX			0x31e
> +		>;
> +	};
> +
> +	pinctrl_uart6: uart6grp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO05__LPUART6_RX			0x31e
> +			MX91_PAD_GPIO_IO04__LPUART6_TX			0x31e
> +		>;
> +	};
> +
> +	pinctrl_uart7: uart7grp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO09__LPUART7_RX			0x31e
> +			MX91_PAD_GPIO_IO08__LPUART7_TX			0x31e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2: usdhc2grp {
> +		fsl,pins = <
> +			MX91_PAD_SD2_CLK__USDHC2_CLK			0x1582
> +			MX91_PAD_SD2_CMD__USDHC2_CMD			0x1382
> +			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x1382
> +			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x1382
> +			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x1382
> +			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x1382
> +			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD2_CLK__USDHC2_CLK			0x158e
> +			MX91_PAD_SD2_CMD__USDHC2_CMD			0x138e
> +			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x138e
> +			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x138e
> +			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x138e
> +			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x138e
> +			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD2_CLK__USDHC2_CLK			0x15fe
> +			MX91_PAD_SD2_CMD__USDHC2_CMD			0x13fe
> +			MX91_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe
> +			MX91_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe
> +			MX91_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe
> +			MX91_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe
> +			MX91_PAD_SD2_VSELECT__USDHC2_VSELECT		0x51e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_sleep: usdhc2sleepgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD2_CLK__GPIO3_IO1			0x51e
> +			MX91_PAD_SD2_CMD__GPIO3_IO2			0x51e
> +			MX91_PAD_SD2_DATA0__GPIO3_IO3			0x51e
> +			MX91_PAD_SD2_DATA1__GPIO3_IO4			0x51e
> +			MX91_PAD_SD2_DATA2__GPIO3_IO5			0x51e
> +			MX91_PAD_SD2_DATA3__GPIO3_IO6			0x51e
> +			MX91_PAD_SD2_VSELECT__GPIO3_IO19		0x51e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
> +		fsl,pins = <
> +			MX91_PAD_SD2_CD_B__GPIO3_IO0			0x31e
> +		>;
> +	};
> +
> +	pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD2_CD_B__GPIO3_IO0			0x51e
> +		>;
> +	};
> +};
> --
> 2.47.3
>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91
  2026-02-05 10:01 ` [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91 Stefano Radaelli
@ 2026-02-05 15:13   ` Frank Li
  2026-03-02 16:30     ` Frank Li
  0 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2026-02-05 15:13 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 05, 2026 at 11:01:24AM +0100, Stefano Radaelli wrote:
> From: Stefano Radaelli <stefano.r@variscite.com>
>
> Add device tree support for the Variscite DART-MX91 system on module.
> This SOM is designed to be used with various carrier boards.
>
> The module includes:
> - NXP i.MX91 MPU processor
> - Up to 2GB of LPDDR4 memory
> - Up to 128GB of eMMC storage memory
> - Integrated 10/100/1000 Mbps Ethernet Transceiver
> - Codec audio WM8904
> - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
>
> Only SOM-specific peripherals are enabled by default. Carrier board
> specific interfaces are left disabled to be enabled in the respective
> carrier board device trees.
>
> Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
> ---
>  .../boot/dts/freescale/imx91-var-dart.dtsi    | 468 ++++++++++++++++++
>  1 file changed, 468 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
> new file mode 100644
> index 000000000000..e87b7abd86bb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
> @@ -0,0 +1,468 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Common dtsi for Variscite DART-MX91
> + *
> + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/
> + *
> + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/leds/common.h>
> +#include <dt-bindings/usb/pd.h>
> +#include "imx91.dtsi"
> +
> +/ {
> +	model = "Variscite DART-MX91 Module";
> +	compatible = "variscite,var-dart-mx91", "fsl,imx91";
> +
> +	sound-wm8904 {
> +		compatible = "simple-audio-card";
> +		simple-audio-card,bitclock-master = <&codec_dai>;
> +		simple-audio-card,format = "i2s";
> +		simple-audio-card,frame-master = <&codec_dai>;
> +		simple-audio-card,mclk-fs = <256>;
> +		simple-audio-card,name = "wm8904-audio";
> +		simple-audio-card,routing =
> +			"Headphone Jack", "HPOUTL",
> +			"Headphone Jack", "HPOUTR",
> +			"IN2L", "Line In Jack",
> +			"IN2R", "Line In Jack",
> +			"IN1L", "Microphone Jack",
> +			"IN1R", "Microphone Jack";
> +		simple-audio-card,widgets =
> +			"Microphone", "Microphone Jack",
> +			"Headphone", "Headphone Jack",
> +			"Line", "Line In Jack";
> +
> +		codec_dai: simple-audio-card,codec {
> +			sound-dai = <&wm8904>;
> +		};
> +
> +		simple-audio-card,cpu {
> +			sound-dai = <&sai1>;
> +		};
> +	};
> +
> +	wifi_pwrseq: wifi-pwrseq {
> +		compatible = "mmc-pwrseq-simple";
> +		post-power-on-delay-ms = <100>;
> +		power-off-delay-us = <10000>;
> +		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
> +			      <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
> +	};
> +};
> +
> +&eqos {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&pinctrl_eqos>;
> +	pinctrl-1 = <&pinctrl_eqos_sleep>;
> +	/*
> +	 * The required RGMII TX and RX 2ns delays are implemented directly
> +	 * in hardware via passive delay elements on the SOM PCB.
> +	 * No delay configuration is needed in software via PHY driver.
> +	 */
> +	phy-mode = "rgmii";
> +	phy-handle = <&ethphy0>;
> +	snps,clk-csr = <5>;
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";
> +		clock-frequency = <1000000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		ethphy0: ethernet-phy@0 {
> +			compatible = "ethernet-phy-ieee802.3-c22";
> +			reg = <0>;
> +			reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> +			reset-assert-us = <15000>;
> +			reset-deassert-us = <100000>;
> +
> +			leds {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				led@0 {
> +					reg = <0>;
> +					color = <LED_COLOR_ID_YELLOW>;
> +					function = LED_FUNCTION_LAN;
> +					linux,default-trigger = "netdev";
> +				};
> +
> +				led@1 {
> +					reg = <1>;
> +					color = <LED_COLOR_ID_GREEN>;
> +					function = LED_FUNCTION_LAN;
> +					linux,default-trigger = "netdev";
> +				};
> +			};
> +		};
> +	};
> +};
> +
> +&lpi2c3 {
> +	clock-frequency = <400000>;
> +	pinctrl-names = "default", "sleep", "gpio";
> +	pinctrl-0 = <&pinctrl_lpi2c3>;
> +	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
> +	pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
> +	scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> +	status = "okay";
> +
> +	wm8904: audio-codec@1a {
> +		compatible = "wlf,wm8904";
> +		reg = <0x1a>;
> +		#sound-dai-cells = <0>;
> +		clocks = <&clk IMX93_CLK_SAI1_GATE>;
> +		clock-names = "mclk";
> +		AVDD-supply = <&buck5>;
> +		CPVDD-supply = <&buck5>;
> +		DBVDD-supply = <&buck4>;
> +		DCVDD-supply = <&buck5>;
> +		MICVDD-supply = <&buck5>;
> +		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
> +				    "soft", "music";
> +		/*
> +		 * Config registers per name, respectively:
> +		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
> +		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
> +		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
> +		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
> +		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
> +		 */
> +		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
> +				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
> +				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
> +				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
> +				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
> +		/* GPIO1 = DMIC_CLK, don't touch others */
> +		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
> +		/* DMIC is connected to IN1L */
> +		wlf,in1l-as-dmicdat1;
> +	};
> +
> +	pmic@25 {
> +		compatible = "nxp,pca9451a";
> +		reg = <0x25>;
> +
> +		regulators {
> +			buck1: BUCK1 {
> +				regulator-name = "BUCK1";
> +				regulator-min-microvolt = <650000>;
> +				regulator-max-microvolt = <2237500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			buck2: BUCK2 {
> +				regulator-name = "BUCK2";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <2187500>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +				regulator-ramp-delay = <3125>;
> +			};
> +
> +			buck4: BUCK4{
> +				regulator-name = "BUCK4";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck5: BUCK5{
> +				regulator-name = "BUCK5";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			buck6: BUCK6 {
> +				regulator-name = "BUCK6";
> +				regulator-min-microvolt = <600000>;
> +				regulator-max-microvolt = <3400000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo1: LDO1 {
> +				regulator-name = "LDO1";
> +				regulator-min-microvolt = <1600000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo4: LDO4 {
> +				regulator-name = "LDO4";
> +				regulator-min-microvolt = <800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +
> +			ldo5: LDO5 {
> +				regulator-name = "LDO5";
> +				regulator-min-microvolt = <1800000>;
> +				regulator-max-microvolt = <3300000>;
> +				regulator-boot-on;
> +				regulator-always-on;
> +			};
> +		};
> +	};
> +};
> +
> +/* BT module */
> +&lpuart5 {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
> +	uart-has-rtscts;
> +	status = "okay";
> +
> +	bluetooth {
> +		compatible = "nxp,88w8987-bt";
> +	};
> +};
> +
> +&sai1 {
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&pinctrl_sai1>;
> +	pinctrl-1 = <&pinctrl_sai1_sleep>;
> +	assigned-clocks = <&clk IMX93_CLK_SAI1>;
> +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> +	assigned-clock-rates = <12288000>;
> +	#sound-dai-cells = <0>;
> +	fsl,sai-mclk-direction-output;
> +	status = "okay";
> +};
> +
> +/* eMMC */
> +&usdhc1 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> +	pinctrl-0 = <&pinctrl_usdhc1>;
> +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> +	bus-width = <8>;
> +	non-removable;
> +	status = "okay";
> +};
> +
> +/* WiFi */
> +&usdhc3 {
> +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> +	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
> +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
> +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
> +	pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
> +	mmc-pwrseq = <&wifi_pwrseq>;
> +	keep-power-in-suspend;
> +	bus-width = <4>;
> +	non-removable;
> +	wakeup-source;
> +	status = "okay";
> +};
> +
> +&wdog3 {
> +	status = "okay";
> +};
> +
> +&iomuxc {
> +	pinctrl_bt: btgrp {
> +		fsl,pins = <
> +			MX91_PAD_ENET2_MDIO__GPIO4_IO15				0x51e
> +		>;
> +	};
> +
> +	pinctrl_eqos: eqosgrp {
> +		fsl,pins = <
> +			MX91_PAD_ENET1_MDC__ENET1_MDC				0x57e
> +			MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
> +			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
> +			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
> +			MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
> +			MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
> +			MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC			0x5fe
> +			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
> +			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
> +			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1			0x57e
> +			MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
> +			MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
> +			MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
> +			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
> +			MX91_PAD_UART2_TXD__GPIO1_IO7				0x51e
> +		>;
> +	};
> +
> +	pinctrl_eqos_sleep: eqos-sleepgrp {
> +		fsl,pins = <
> +			MX91_PAD_ENET1_MDC__GPIO4_IO0				0x31e
> +			MX91_PAD_ENET1_MDIO__GPIO4_IO1				0x31e
> +			MX91_PAD_ENET1_RD0__GPIO4_IO10				0x31e
> +			MX91_PAD_ENET1_RD1__GPIO4_IO11				0x31e
> +			MX91_PAD_ENET1_RD2__GPIO4_IO12				0x31e
> +			MX91_PAD_ENET1_RD3__GPIO4_IO13				0x31e
> +			MX91_PAD_ENET1_RXC__GPIO4_IO9				0x31e
> +			MX91_PAD_ENET1_RX_CTL__GPIO4_IO8			0x31e
> +			MX91_PAD_ENET1_TD0__GPIO4_IO5				0x31e
> +			MX91_PAD_ENET1_TD1__GPIO4_IO4				0x31e
> +			MX91_PAD_ENET1_TD2__GPIO4_IO3				0x31e
> +			MX91_PAD_ENET1_TD3__GPIO4_IO2				0x31e
> +			MX91_PAD_ENET1_TXC__GPIO4_IO7				0x31e
> +			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6			0x31e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c3: lpi2c3grp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO28__LPI2C3_SDA				0x40000b9e
> +			MX91_PAD_GPIO_IO29__LPI2C3_SCL				0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
> +		fsl,pins = <
> +			MX91_PAD_GPIO_IO28__GPIO2_IO28				0x40000b9e
> +			MX91_PAD_GPIO_IO29__GPIO2_IO29				0x40000b9e
> +		>;
> +	};
> +
> +	pinctrl_sai1: sai1grp {
> +		fsl,pins = <
> +			MX91_PAD_SAI1_TXC__SAI1_TX_BCLK				0x31e
> +			MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC			0x31e
> +			MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0			0x31e
> +			MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0			0x31e
> +			MX91_PAD_I2C2_SDA__SAI1_RX_BCLK				0x31e
> +			MX91_PAD_I2C2_SCL__SAI1_RX_SYNC				0x31e
> +			MX91_PAD_UART2_RXD__SAI1_MCLK				0x31e
> +		>;
> +	};
> +
> +	pinctrl_sai1_sleep: sai1-sleepgrp {
> +		fsl,pins = <
> +			MX91_PAD_SAI1_TXC__GPIO1_IO12				0x31e
> +			MX91_PAD_SAI1_TXFS__GPIO1_IO11				0x31e
> +			MX91_PAD_SAI1_TXD0__GPIO1_IO13				0x31e
> +			MX91_PAD_SAI1_RXD0__GPIO1_IO14				0x31e
> +			MX91_PAD_UART2_RXD__GPIO1_IO6				0x31e
> +			MX91_PAD_I2C2_SDA__GPIO1_IO3				0x31e
> +			MX91_PAD_I2C2_SCL__GPIO1_IO2				0x31e
> +		>;
> +	};
> +
> +	pinctrl_uart5: uart5grp {
> +		fsl,pins = <
> +			MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX			0x31e
> +			MX91_PAD_DAP_TDI__LPUART5_RX				0x31e
> +			MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B			0x31e
> +			MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B			0x31e
> +		>;
> +	};
> +
> +	pinctrl_usdhc1: usdhc1grp {
> +		fsl,pins = <
> +			MX91_PAD_SD1_CLK__USDHC1_CLK				0x1582
> +			MX91_PAD_SD1_CMD__USDHC1_CMD				0x1382
> +			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x1382
> +			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x1382
> +			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x1382
> +			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x1382
> +			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x1382
> +			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x1382
> +			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x1382
> +			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x1382
> +			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x1582
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD1_CLK__USDHC1_CLK				0x158e
> +			MX91_PAD_SD1_CMD__USDHC1_CMD				0x138e
> +			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x138e
> +			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x138e
> +			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x138e
> +			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x138e
> +			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x138e
> +			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x138e
> +			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x138e
> +			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x138e
> +			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x158e
> +		>;
> +	};
> +
> +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD1_CLK__USDHC1_CLK				0x15fe
> +			MX91_PAD_SD1_CMD__USDHC1_CMD				0x13fe
> +			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe
> +			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe
> +			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe
> +			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe
> +			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe
> +			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe
> +			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe
> +			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe
> +			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe
> +		>;
> +	};
> +
> +	pinctrl_usdhc3: usdhc3grp {
> +		fsl,pins = <
> +			MX91_PAD_SD3_CLK__USDHC3_CLK				0x1582
> +			MX91_PAD_SD3_CMD__USDHC3_CMD				0x1382
> +			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x1382
> +			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x1382
> +			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x1382
> +			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x1382
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD3_CLK__USDHC3_CLK				0x158e
> +			MX91_PAD_SD3_CMD__USDHC3_CMD				0x138e
> +			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x138e
> +			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x138e
> +			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x138e
> +			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x138e
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD3_CLK__USDHC3_CLK				0x15fe
> +			MX91_PAD_SD3_CMD__USDHC3_CMD				0x13fe
> +			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x13fe
> +			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x13fe
> +			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x13fe
> +			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x13fe
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
> +		fsl,pins = <
> +			MX91_PAD_SD3_CLK__GPIO3_IO20				0x31e
> +			MX91_PAD_SD3_CMD__GPIO3_IO21				0x31e
> +			MX91_PAD_SD3_DATA0__GPIO3_IO22				0x31e
> +			MX91_PAD_SD3_DATA1__GPIO3_IO23				0x31e
> +			MX91_PAD_SD3_DATA2__GPIO3_IO24				0x31e
> +			MX91_PAD_SD3_DATA3__GPIO3_IO25				0x31e
> +		>;
> +	};
> +
> +	pinctrl_usdhc3_wlan: usdhc3wlangrp {
> +		fsl,pins = <
> +			MX91_PAD_ENET2_MDC__GPIO4_IO14				0x51e
> +			MX91_PAD_SD2_RESET_B__GPIO3_IO7				0x51e
> +		>;
> +	};
> +};
> --
> 2.47.3
>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board
  2026-02-05 15:09 ` Frank Li
@ 2026-02-05 15:18   ` Stefano Radaelli
  2026-02-05 16:38     ` Frank Li
  0 siblings, 1 reply; 15+ messages in thread
From: Stefano Radaelli @ 2026-02-05 15:18 UTC (permalink / raw)
  To: Frank Li
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 05, 2026 at 10:09:06AM -0500, Frank Li wrote:
> 
> where your v2 change log?
> 
> Frank
> >

Hi,

thanks for pointing that out, my mistake.

Would you prefer me to resend the same v2 series with an updated
v2 changelog in the cover letter, or handle it differently?

Best regards,
Stefano


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board
  2026-02-05 15:18   ` Stefano Radaelli
@ 2026-02-05 16:38     ` Frank Li
  0 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2026-02-05 16:38 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 05, 2026 at 04:18:07PM +0100, Stefano Radaelli wrote:
> On Thu, Feb 05, 2026 at 10:09:06AM -0500, Frank Li wrote:
> >
> > where your v2 change log?
> >
> > Frank
> > >
>
> Hi,
>
> thanks for pointing that out, my mistake.
>
> Would you prefer me to resend the same v2 series with an updated
> v2 changelog in the cover letter, or handle it differently?

Needn't resend if no update of patch, Just reminder you to add change log
next time.

Frank
>
> Best regards,
> Stefano


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: (subset) [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board
  2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
                   ` (4 preceding siblings ...)
  2026-02-05 15:09 ` Frank Li
@ 2026-03-02 16:24 ` Frank Li
  5 siblings, 0 replies; 15+ messages in thread
From: Frank Li @ 2026-03-02 16:24 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	Stefano Radaelli
  Cc: Frank Li, kernel, festevam, alexander.stein, dario.binacchi,
	primoz.fiser, Markus.Niebel, y.moog, josua, francesco.dolcini,
	maudspierings, pierluigi.p, Stefano Radaelli


On Thu, 05 Feb 2026 11:01:22 +0100, Stefano Radaelli wrote:
> This patch series adds support for the Variscite DART-MX91 system on
> module and the Sonata carrier board.
> 
> The series includes:
> - Device tree bindings documentation for both SOM and carrier board
> - SOM device tree with on-module peripherals
> - Sonata carrier board device tree with board-specific features
> 
> [...]

Applied, thanks!

[1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards
      (no commit info)

Best regards,
--
Frank Li <Frank.Li@nxp.com>


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91
  2026-02-05 15:13   ` Frank Li
@ 2026-03-02 16:30     ` Frank Li
  2026-03-02 17:02       ` Stefano Radaelli
  0 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2026-03-02 16:30 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Thu, Feb 05, 2026 at 10:13:05AM -0500, Frank Li wrote:
> On Thu, Feb 05, 2026 at 11:01:24AM +0100, Stefano Radaelli wrote:
> > From: Stefano Radaelli <stefano.r@variscite.com>
> >
> > Add device tree support for the Variscite DART-MX91 system on module.
> > This SOM is designed to be used with various carrier boards.
> >
> > The module includes:
> > - NXP i.MX91 MPU processor
> > - Up to 2GB of LPDDR4 memory
> > - Up to 128GB of eMMC storage memory
> > - Integrated 10/100/1000 Mbps Ethernet Transceiver
> > - Codec audio WM8904
> > - WIFI6 dual-band 802.11ax/ac/a/b/g/n with optional 802.15.4 and Bluetooth
> >
> > Only SOM-specific peripherals are enabled by default. Carrier board
> > specific interfaces are left disabled to be enabled in the respective
> > carrier board device trees.
> >
> > Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/
> Reviewed-by: Frank Li <Frank.Li@nxp.com>

dts part can't apply, please rebase.

Frank
> >
> > Signed-off-by: Stefano Radaelli <stefano.r@variscite.com>
> > ---
> >  .../boot/dts/freescale/imx91-var-dart.dtsi    | 468 ++++++++++++++++++
> >  1 file changed, 468 insertions(+)
> >  create mode 100644 arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
> > new file mode 100644
> > index 000000000000..e87b7abd86bb
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx91-var-dart.dtsi
> > @@ -0,0 +1,468 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Common dtsi for Variscite DART-MX91
> > + *
> > + * Link: https://variscite.com/system-on-module-som/i-mx-9/i-mx-91/dart-mx91/
> > + *
> > + * Copyright (C) 2026 Variscite Ltd. - https://www.variscite.com/
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/leds/common.h>
> > +#include <dt-bindings/usb/pd.h>
> > +#include "imx91.dtsi"
> > +
> > +/ {
> > +	model = "Variscite DART-MX91 Module";
> > +	compatible = "variscite,var-dart-mx91", "fsl,imx91";
> > +
> > +	sound-wm8904 {
> > +		compatible = "simple-audio-card";
> > +		simple-audio-card,bitclock-master = <&codec_dai>;
> > +		simple-audio-card,format = "i2s";
> > +		simple-audio-card,frame-master = <&codec_dai>;
> > +		simple-audio-card,mclk-fs = <256>;
> > +		simple-audio-card,name = "wm8904-audio";
> > +		simple-audio-card,routing =
> > +			"Headphone Jack", "HPOUTL",
> > +			"Headphone Jack", "HPOUTR",
> > +			"IN2L", "Line In Jack",
> > +			"IN2R", "Line In Jack",
> > +			"IN1L", "Microphone Jack",
> > +			"IN1R", "Microphone Jack";
> > +		simple-audio-card,widgets =
> > +			"Microphone", "Microphone Jack",
> > +			"Headphone", "Headphone Jack",
> > +			"Line", "Line In Jack";
> > +
> > +		codec_dai: simple-audio-card,codec {
> > +			sound-dai = <&wm8904>;
> > +		};
> > +
> > +		simple-audio-card,cpu {
> > +			sound-dai = <&sai1>;
> > +		};
> > +	};
> > +
> > +	wifi_pwrseq: wifi-pwrseq {
> > +		compatible = "mmc-pwrseq-simple";
> > +		post-power-on-delay-ms = <100>;
> > +		power-off-delay-us = <10000>;
> > +		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
> > +			      <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
> > +	};
> > +};
> > +
> > +&eqos {
> > +	pinctrl-names = "default", "sleep";
> > +	pinctrl-0 = <&pinctrl_eqos>;
> > +	pinctrl-1 = <&pinctrl_eqos_sleep>;
> > +	/*
> > +	 * The required RGMII TX and RX 2ns delays are implemented directly
> > +	 * in hardware via passive delay elements on the SOM PCB.
> > +	 * No delay configuration is needed in software via PHY driver.
> > +	 */
> > +	phy-mode = "rgmii";
> > +	phy-handle = <&ethphy0>;
> > +	snps,clk-csr = <5>;
> > +	status = "okay";
> > +
> > +	mdio {
> > +		compatible = "snps,dwmac-mdio";
> > +		clock-frequency = <1000000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +
> > +		ethphy0: ethernet-phy@0 {
> > +			compatible = "ethernet-phy-ieee802.3-c22";
> > +			reg = <0>;
> > +			reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
> > +			reset-assert-us = <15000>;
> > +			reset-deassert-us = <100000>;
> > +
> > +			leds {
> > +				#address-cells = <1>;
> > +				#size-cells = <0>;
> > +
> > +				led@0 {
> > +					reg = <0>;
> > +					color = <LED_COLOR_ID_YELLOW>;
> > +					function = LED_FUNCTION_LAN;
> > +					linux,default-trigger = "netdev";
> > +				};
> > +
> > +				led@1 {
> > +					reg = <1>;
> > +					color = <LED_COLOR_ID_GREEN>;
> > +					function = LED_FUNCTION_LAN;
> > +					linux,default-trigger = "netdev";
> > +				};
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > +&lpi2c3 {
> > +	clock-frequency = <400000>;
> > +	pinctrl-names = "default", "sleep", "gpio";
> > +	pinctrl-0 = <&pinctrl_lpi2c3>;
> > +	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
> > +	pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
> > +	scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > +	sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
> > +	status = "okay";
> > +
> > +	wm8904: audio-codec@1a {
> > +		compatible = "wlf,wm8904";
> > +		reg = <0x1a>;
> > +		#sound-dai-cells = <0>;
> > +		clocks = <&clk IMX93_CLK_SAI1_GATE>;
> > +		clock-names = "mclk";
> > +		AVDD-supply = <&buck5>;
> > +		CPVDD-supply = <&buck5>;
> > +		DBVDD-supply = <&buck4>;
> > +		DCVDD-supply = <&buck5>;
> > +		MICVDD-supply = <&buck5>;
> > +		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
> > +				    "soft", "music";
> > +		/*
> > +		 * Config registers per name, respectively:
> > +		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
> > +		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
> > +		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
> > +		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
> > +		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
> > +		 */
> > +		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
> > +				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
> > +				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
> > +				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
> > +				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
> > +		/* GPIO1 = DMIC_CLK, don't touch others */
> > +		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
> > +		/* DMIC is connected to IN1L */
> > +		wlf,in1l-as-dmicdat1;
> > +	};
> > +
> > +	pmic@25 {
> > +		compatible = "nxp,pca9451a";
> > +		reg = <0x25>;
> > +
> > +		regulators {
> > +			buck1: BUCK1 {
> > +				regulator-name = "BUCK1";
> > +				regulator-min-microvolt = <650000>;
> > +				regulator-max-microvolt = <2237500>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +				regulator-ramp-delay = <3125>;
> > +			};
> > +
> > +			buck2: BUCK2 {
> > +				regulator-name = "BUCK2";
> > +				regulator-min-microvolt = <600000>;
> > +				regulator-max-microvolt = <2187500>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +				regulator-ramp-delay = <3125>;
> > +			};
> > +
> > +			buck4: BUCK4{
> > +				regulator-name = "BUCK4";
> > +				regulator-min-microvolt = <600000>;
> > +				regulator-max-microvolt = <3400000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +
> > +			buck5: BUCK5{
> > +				regulator-name = "BUCK5";
> > +				regulator-min-microvolt = <600000>;
> > +				regulator-max-microvolt = <3400000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +
> > +			buck6: BUCK6 {
> > +				regulator-name = "BUCK6";
> > +				regulator-min-microvolt = <600000>;
> > +				regulator-max-microvolt = <3400000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +
> > +			ldo1: LDO1 {
> > +				regulator-name = "LDO1";
> > +				regulator-min-microvolt = <1600000>;
> > +				regulator-max-microvolt = <3300000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +
> > +			ldo4: LDO4 {
> > +				regulator-name = "LDO4";
> > +				regulator-min-microvolt = <800000>;
> > +				regulator-max-microvolt = <3300000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +
> > +			ldo5: LDO5 {
> > +				regulator-name = "LDO5";
> > +				regulator-min-microvolt = <1800000>;
> > +				regulator-max-microvolt = <3300000>;
> > +				regulator-boot-on;
> > +				regulator-always-on;
> > +			};
> > +		};
> > +	};
> > +};
> > +
> > +/* BT module */
> > +&lpuart5 {
> > +	pinctrl-names = "default";
> > +	pinctrl-0 = <&pinctrl_uart5>, <&pinctrl_bt>;
> > +	uart-has-rtscts;
> > +	status = "okay";
> > +
> > +	bluetooth {
> > +		compatible = "nxp,88w8987-bt";
> > +	};
> > +};
> > +
> > +&sai1 {
> > +	pinctrl-names = "default", "sleep";
> > +	pinctrl-0 = <&pinctrl_sai1>;
> > +	pinctrl-1 = <&pinctrl_sai1_sleep>;
> > +	assigned-clocks = <&clk IMX93_CLK_SAI1>;
> > +	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
> > +	assigned-clock-rates = <12288000>;
> > +	#sound-dai-cells = <0>;
> > +	fsl,sai-mclk-direction-output;
> > +	status = "okay";
> > +};
> > +
> > +/* eMMC */
> > +&usdhc1 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz";
> > +	pinctrl-0 = <&pinctrl_usdhc1>;
> > +	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
> > +	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
> > +	bus-width = <8>;
> > +	non-removable;
> > +	status = "okay";
> > +};
> > +
> > +/* WiFi */
> > +&usdhc3 {
> > +	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
> > +	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
> > +	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
> > +	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
> > +	pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
> > +	mmc-pwrseq = <&wifi_pwrseq>;
> > +	keep-power-in-suspend;
> > +	bus-width = <4>;
> > +	non-removable;
> > +	wakeup-source;
> > +	status = "okay";
> > +};
> > +
> > +&wdog3 {
> > +	status = "okay";
> > +};
> > +
> > +&iomuxc {
> > +	pinctrl_bt: btgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_ENET2_MDIO__GPIO4_IO15				0x51e
> > +		>;
> > +	};
> > +
> > +	pinctrl_eqos: eqosgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_ENET1_MDC__ENET1_MDC				0x57e
> > +			MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
> > +			MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
> > +			MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
> > +			MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
> > +			MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
> > +			MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC			0x5fe
> > +			MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
> > +			MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
> > +			MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1			0x57e
> > +			MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
> > +			MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
> > +			MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x5fe
> > +			MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
> > +			MX91_PAD_UART2_TXD__GPIO1_IO7				0x51e
> > +		>;
> > +	};
> > +
> > +	pinctrl_eqos_sleep: eqos-sleepgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_ENET1_MDC__GPIO4_IO0				0x31e
> > +			MX91_PAD_ENET1_MDIO__GPIO4_IO1				0x31e
> > +			MX91_PAD_ENET1_RD0__GPIO4_IO10				0x31e
> > +			MX91_PAD_ENET1_RD1__GPIO4_IO11				0x31e
> > +			MX91_PAD_ENET1_RD2__GPIO4_IO12				0x31e
> > +			MX91_PAD_ENET1_RD3__GPIO4_IO13				0x31e
> > +			MX91_PAD_ENET1_RXC__GPIO4_IO9				0x31e
> > +			MX91_PAD_ENET1_RX_CTL__GPIO4_IO8			0x31e
> > +			MX91_PAD_ENET1_TD0__GPIO4_IO5				0x31e
> > +			MX91_PAD_ENET1_TD1__GPIO4_IO4				0x31e
> > +			MX91_PAD_ENET1_TD2__GPIO4_IO3				0x31e
> > +			MX91_PAD_ENET1_TD3__GPIO4_IO2				0x31e
> > +			MX91_PAD_ENET1_TXC__GPIO4_IO7				0x31e
> > +			MX91_PAD_ENET1_TX_CTL__GPIO4_IO6			0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_lpi2c3: lpi2c3grp {
> > +		fsl,pins = <
> > +			MX91_PAD_GPIO_IO28__LPI2C3_SDA				0x40000b9e
> > +			MX91_PAD_GPIO_IO29__LPI2C3_SCL				0x40000b9e
> > +		>;
> > +	};
> > +
> > +	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
> > +		fsl,pins = <
> > +			MX91_PAD_GPIO_IO28__GPIO2_IO28				0x40000b9e
> > +			MX91_PAD_GPIO_IO29__GPIO2_IO29				0x40000b9e
> > +		>;
> > +	};
> > +
> > +	pinctrl_sai1: sai1grp {
> > +		fsl,pins = <
> > +			MX91_PAD_SAI1_TXC__SAI1_TX_BCLK				0x31e
> > +			MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC			0x31e
> > +			MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0			0x31e
> > +			MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0			0x31e
> > +			MX91_PAD_I2C2_SDA__SAI1_RX_BCLK				0x31e
> > +			MX91_PAD_I2C2_SCL__SAI1_RX_SYNC				0x31e
> > +			MX91_PAD_UART2_RXD__SAI1_MCLK				0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_sai1_sleep: sai1-sleepgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_SAI1_TXC__GPIO1_IO12				0x31e
> > +			MX91_PAD_SAI1_TXFS__GPIO1_IO11				0x31e
> > +			MX91_PAD_SAI1_TXD0__GPIO1_IO13				0x31e
> > +			MX91_PAD_SAI1_RXD0__GPIO1_IO14				0x31e
> > +			MX91_PAD_UART2_RXD__GPIO1_IO6				0x31e
> > +			MX91_PAD_I2C2_SDA__GPIO1_IO3				0x31e
> > +			MX91_PAD_I2C2_SCL__GPIO1_IO2				0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_uart5: uart5grp {
> > +		fsl,pins = <
> > +			MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX			0x31e
> > +			MX91_PAD_DAP_TDI__LPUART5_RX				0x31e
> > +			MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B			0x31e
> > +			MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B			0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1: usdhc1grp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD1_CLK__USDHC1_CLK				0x1582
> > +			MX91_PAD_SD1_CMD__USDHC1_CMD				0x1382
> > +			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x1382
> > +			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x1382
> > +			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x1382
> > +			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x1382
> > +			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x1382
> > +			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x1382
> > +			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x1382
> > +			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x1382
> > +			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x1582
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD1_CLK__USDHC1_CLK				0x158e
> > +			MX91_PAD_SD1_CMD__USDHC1_CMD				0x138e
> > +			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x138e
> > +			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x138e
> > +			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x138e
> > +			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x138e
> > +			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x138e
> > +			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x138e
> > +			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x138e
> > +			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x138e
> > +			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x158e
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD1_CLK__USDHC1_CLK				0x15fe
> > +			MX91_PAD_SD1_CMD__USDHC1_CMD				0x13fe
> > +			MX91_PAD_SD1_DATA0__USDHC1_DATA0			0x13fe
> > +			MX91_PAD_SD1_DATA1__USDHC1_DATA1			0x13fe
> > +			MX91_PAD_SD1_DATA2__USDHC1_DATA2			0x13fe
> > +			MX91_PAD_SD1_DATA3__USDHC1_DATA3			0x13fe
> > +			MX91_PAD_SD1_DATA4__USDHC1_DATA4			0x13fe
> > +			MX91_PAD_SD1_DATA5__USDHC1_DATA5			0x13fe
> > +			MX91_PAD_SD1_DATA6__USDHC1_DATA6			0x13fe
> > +			MX91_PAD_SD1_DATA7__USDHC1_DATA7			0x13fe
> > +			MX91_PAD_SD1_STROBE__USDHC1_STROBE			0x15fe
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3: usdhc3grp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD3_CLK__USDHC3_CLK				0x1582
> > +			MX91_PAD_SD3_CMD__USDHC3_CMD				0x1382
> > +			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x1382
> > +			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x1382
> > +			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x1382
> > +			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x1382
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD3_CLK__USDHC3_CLK				0x158e
> > +			MX91_PAD_SD3_CMD__USDHC3_CMD				0x138e
> > +			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x138e
> > +			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x138e
> > +			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x138e
> > +			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x138e
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD3_CLK__USDHC3_CLK				0x15fe
> > +			MX91_PAD_SD3_CMD__USDHC3_CMD				0x13fe
> > +			MX91_PAD_SD3_DATA0__USDHC3_DATA0			0x13fe
> > +			MX91_PAD_SD3_DATA1__USDHC3_DATA1			0x13fe
> > +			MX91_PAD_SD3_DATA2__USDHC3_DATA2			0x13fe
> > +			MX91_PAD_SD3_DATA3__USDHC3_DATA3			0x13fe
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
> > +		fsl,pins = <
> > +			MX91_PAD_SD3_CLK__GPIO3_IO20				0x31e
> > +			MX91_PAD_SD3_CMD__GPIO3_IO21				0x31e
> > +			MX91_PAD_SD3_DATA0__GPIO3_IO22				0x31e
> > +			MX91_PAD_SD3_DATA1__GPIO3_IO23				0x31e
> > +			MX91_PAD_SD3_DATA2__GPIO3_IO24				0x31e
> > +			MX91_PAD_SD3_DATA3__GPIO3_IO25				0x31e
> > +		>;
> > +	};
> > +
> > +	pinctrl_usdhc3_wlan: usdhc3wlangrp {
> > +		fsl,pins = <
> > +			MX91_PAD_ENET2_MDC__GPIO4_IO14				0x51e
> > +			MX91_PAD_SD2_RESET_B__GPIO3_IO7				0x51e
> > +		>;
> > +	};
> > +};
> > --
> > 2.47.3
> >


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91
  2026-03-02 16:30     ` Frank Li
@ 2026-03-02 17:02       ` Stefano Radaelli
  2026-03-02 21:35         ` Frank Li
  0 siblings, 1 reply; 15+ messages in thread
From: Stefano Radaelli @ 2026-03-02 17:02 UTC (permalink / raw)
  To: Frank Li
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

Hi Frank

On Mon, Mar 02, 2026 at 11:30:10AM -0500, Frank Li wrote:
> 
> dts part can't apply, please rebase.
> 

Thanks for the feedback.

I rebased the series on top of the current mainline (Linux master tree) and
it applies cleanly on my side.

Could you please let me know which specific tree/branch I should rebase
onto for the DTS changes? I will respin the series accordingly.

Best regards,
Stefano


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91
  2026-03-02 17:02       ` Stefano Radaelli
@ 2026-03-02 21:35         ` Frank Li
  2026-03-03 10:24           ` Stefano Radaelli
  0 siblings, 1 reply; 15+ messages in thread
From: Frank Li @ 2026-03-02 21:35 UTC (permalink / raw)
  To: Stefano Radaelli
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Mon, Mar 02, 2026 at 06:02:10PM +0100, Stefano Radaelli wrote:
> Hi Frank
>
> On Mon, Mar 02, 2026 at 11:30:10AM -0500, Frank Li wrote:
> >
> > dts part can't apply, please rebase.
> >
>
> Thanks for the feedback.
>
> I rebased the series on top of the current mainline (Linux master tree) and
> it applies cleanly on my side.
>
> Could you please let me know which specific tree/branch I should rebase
> onto for the DTS changes? I will respin the series accordingly.

https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git/log/?h=imx/dt64

Frank
>
> Best regards,
> Stefano


^ permalink raw reply	[flat|nested] 15+ messages in thread

* Re: [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91
  2026-03-02 21:35         ` Frank Li
@ 2026-03-03 10:24           ` Stefano Radaelli
  0 siblings, 0 replies; 15+ messages in thread
From: Stefano Radaelli @ 2026-03-03 10:24 UTC (permalink / raw)
  To: Frank Li
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Shawn Guo,
	Sascha Hauer, linux-kernel, devicetree, imx, linux-arm-kernel,
	kernel, festevam, alexander.stein, dario.binacchi, primoz.fiser,
	Markus.Niebel, y.moog, josua, francesco.dolcini, maudspierings,
	pierluigi.p, Stefano Radaelli

On Mon, Mar 02, 2026 at 04:35:39PM -0500, Frank Li wrote:
> On Mon, Mar 02, 2026 at 06:02:10PM +0100, Stefano Radaelli wrote:
> > Hi Frank
> >
> > On Mon, Mar 02, 2026 at 11:30:10AM -0500, Frank Li wrote:
> > >
> > > dts part can't apply, please rebase.
> > >
> >
> > Thanks for the feedback.
> >
> > I rebased the series on top of the current mainline (Linux master tree) and
> > it applies cleanly on my side.
> >
> > Could you please let me know which specific tree/branch I should rebase
> > onto for the DTS changes? I will respin the series accordingly.
> 
> https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git/log/?h=imx/dt64
> 
> Frank
> >
> > Best regards,
> > Stefano

Thank you Frank,

I'm sending the new revision on top of that.

BR,
Stefano


^ permalink raw reply	[flat|nested] 15+ messages in thread

end of thread, other threads:[~2026-03-03 10:24 UTC | newest]

Thread overview: 15+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-02-05 10:01 [PATCH v2 0/3] Add support for Variscite DART-MX91 and Sonata board Stefano Radaelli
2026-02-05 10:01 ` [PATCH v2 1/3] dt-bindings: arm: fsl: add Variscite DART-MX91 Boards Stefano Radaelli
2026-02-05 10:01 ` [PATCH v2 2/3] arm64: dts: freescale: Add support for Variscite DART-MX91 Stefano Radaelli
2026-02-05 15:13   ` Frank Li
2026-03-02 16:30     ` Frank Li
2026-03-02 17:02       ` Stefano Radaelli
2026-03-02 21:35         ` Frank Li
2026-03-03 10:24           ` Stefano Radaelli
2026-02-05 10:01 ` [PATCH v2 3/3] arm64: dts: imx91-var-dart: Add support for Variscite Sonata board Stefano Radaelli
2026-02-05 15:12   ` Frank Li
2026-02-05 10:14 ` [PATCH v2 0/3] Add support for Variscite DART-MX91 and " Daniel Baluta
2026-02-05 15:09 ` Frank Li
2026-02-05 15:18   ` Stefano Radaelli
2026-02-05 16:38     ` Frank Li
2026-03-02 16:24 ` (subset) " Frank Li

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