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01 Jun 2020 00:24:32 -0700 Subject: Re: [PATCH v8 2/3] perf auxtrace: Add four itrace options To: Leo Yan , Arnaldo Carvalho de Melo , Jiri Olsa , Mark Rutland , Alexander Shishkin , Will Deacon , James Clark , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Andi Kleen , Jin Yao , Ian Rogers , Thomas Gleixner , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Al Grant , Mathieu Poirier , Mike Leach References: <20200530122442.490-1-leo.yan@linaro.org> <20200530122442.490-3-leo.yan@linaro.org> From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: PL 281, 00181 Helsinki, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Message-ID: Date: Mon, 1 Jun 2020 10:24:00 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20200530122442.490-3-leo.yan@linaro.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200601_002440_201593_54D468A7 X-CRM114-Status: GOOD ( 20.50 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tan Xiaojun Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 30/05/20 3:24 pm, Leo Yan wrote: > From: Tan Xiaojun > > This patch is to add four options to synthesize events which are > described as below: > > 'f': synthesize first level cache events > 'm': synthesize last level cache events > 't': synthesize TLB events > 'a': synthesize remote access events > > This four options will be used by ARM SPE as their first consumer. > > Signed-off-by: Tan Xiaojun > Signed-off-by: James Clark > Signed-off-by: Leo Yan > Tested-by: James Clark Acked-by: Adrian Hunter > --- > tools/perf/Documentation/itrace.txt | 6 +++++- > tools/perf/util/auxtrace.c | 17 +++++++++++++++++ > tools/perf/util/auxtrace.h | 15 ++++++++++++++- > 3 files changed, 36 insertions(+), 2 deletions(-) > > diff --git a/tools/perf/Documentation/itrace.txt b/tools/perf/Documentation/itrace.txt > index 271484754fee..e817179c5027 100644 > --- a/tools/perf/Documentation/itrace.txt > +++ b/tools/perf/Documentation/itrace.txt > @@ -1,5 +1,5 @@ > i synthesize instructions events > - b synthesize branches events > + b synthesize branches events (branch misses for Arm SPE) > c synthesize branches events (calls only) > r synthesize branches events (returns only) > x synthesize transactions events > @@ -9,6 +9,10 @@ > of aux-output (refer to perf record) > e synthesize error events > d create a debug log > + f synthesize first level cache events > + m synthesize last level cache events > + t synthesize TLB events > + a synthesize remote access events > g synthesize a call chain (use with i or x) > G synthesize a call chain on existing event records > l synthesize last branch entries (use with i or x) > diff --git a/tools/perf/util/auxtrace.c b/tools/perf/util/auxtrace.c > index 8cf7d405ee67..fe76a056a179 100644 > --- a/tools/perf/util/auxtrace.c > +++ b/tools/perf/util/auxtrace.c > @@ -1331,6 +1331,11 @@ void itrace_synth_opts__set_default(struct itrace_synth_opts *synth_opts, > synth_opts->pwr_events = true; > synth_opts->other_events = true; > synth_opts->errors = true; > + synth_opts->flc = true; > + synth_opts->llc = true; > + synth_opts->tlb = true; > + synth_opts->remote_access = true; > + > if (no_sample) { > synth_opts->period_type = PERF_ITRACE_PERIOD_INSTRUCTIONS; > synth_opts->period = 1; > @@ -1491,6 +1496,18 @@ int itrace_parse_synth_opts(const struct option *opt, const char *str, > goto out_err; > p = endptr; > break; > + case 'f': > + synth_opts->flc = true; > + break; > + case 'm': > + synth_opts->llc = true; > + break; > + case 't': > + synth_opts->tlb = true; > + break; > + case 'a': > + synth_opts->remote_access = true; > + break; > case ' ': > case ',': > break; > diff --git a/tools/perf/util/auxtrace.h b/tools/perf/util/auxtrace.h > index 0220a2e86c16..142ccf7d34df 100644 > --- a/tools/perf/util/auxtrace.h > +++ b/tools/perf/util/auxtrace.h > @@ -63,6 +63,7 @@ enum itrace_period_type { > * because 'perf inject' will write it out > * @instructions: whether to synthesize 'instructions' events > * @branches: whether to synthesize 'branches' events > + * (branch misses only for Arm SPE) > * @transactions: whether to synthesize events for transactions > * @ptwrites: whether to synthesize events for ptwrites > * @pwr_events: whether to synthesize power events > @@ -78,6 +79,10 @@ enum itrace_period_type { > * @thread_stack: feed branches to the thread_stack > * @last_branch: add branch context to 'instruction' events > * @add_last_branch: add branch context to existing event records > + * @flc: whether to synthesize first level cache events > + * @llc: whether to synthesize last level cache events > + * @tlb: whether to synthesize TLB events > + * @remote_access: whether to synthesize remote access events > * @callchain_sz: maximum callchain size > * @last_branch_sz: branch context size > * @period: 'instructions' events period > @@ -107,6 +112,10 @@ struct itrace_synth_opts { > bool thread_stack; > bool last_branch; > bool add_last_branch; > + bool flc; > + bool llc; > + bool tlb; > + bool remote_access; > unsigned int callchain_sz; > unsigned int last_branch_sz; > unsigned long long period; > @@ -596,7 +605,7 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *session, > > #define ITRACE_HELP \ > " i: synthesize instructions events\n" \ > -" b: synthesize branches events\n" \ > +" b: synthesize branches events (branch misses for Arm SPE)\n" \ > " c: synthesize branches events (calls only)\n" \ > " r: synthesize branches events (returns only)\n" \ > " x: synthesize transactions events\n" \ > @@ -604,6 +613,10 @@ bool auxtrace__evsel_is_auxtrace(struct perf_session *session, > " p: synthesize power events\n" \ > " e: synthesize error events\n" \ > " d: create a debug log\n" \ > +" f: synthesize first level cache events\n" \ > +" m: synthesize last level cache events\n" \ > +" t: synthesize TLB events\n" \ > +" a: synthesize remote access events\n" \ > " g[len]: synthesize a call chain (use with i or x)\n" \ > " l[len]: synthesize last branch entries (use with i or x)\n" \ > " sNUMBER: skip initial number of events\n" \ > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel