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Tue, 03 Mar 2026 01:14:10 -0800 (PST) Received: from eichest-laptop ([77.109.188.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-483bd7030b9sm376259165e9.4.2026.03.03.01.14.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Mar 2026 01:14:10 -0800 (PST) Date: Tue, 3 Mar 2026 10:14:08 +0100 From: Stefan Eichenberger To: Frank Li Cc: o.rempel@pengutronix.de, kernel@pengutronix.de, andi.shyti@kernel.org, s.hauer@pengutronix.de, festevam@gmail.com, stefan.eichenberger@toradex.com, francesco.dolcini@toradex.com, linux-i2c@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: Re: [PATCH v1 2/2] i2c: imx: ensure no clock is generated after last read Message-ID: References: <20260218150940.131354-1-eichest@gmail.com> <20260218150940.131354-3-eichest@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260303_011413_245409_C969765D X-CRM114-Status: GOOD ( 18.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Frank, On Wed, Feb 18, 2026 at 05:37:54PM +0100, Stefan Eichenberger wrote: > Hi Frank, > > On Wed, Feb 18, 2026 at 11:26:52AM -0500, Frank Li wrote: > > On Wed, Feb 18, 2026 at 04:08:50PM +0100, Stefan Eichenberger wrote: > > > From: Stefan Eichenberger > > > > > > When reading from the I2DR register, right after releasing the bus by > > > clearing MSTA and MTX, the I2C controller might still generate an > > > additional clock cycle which can cause devices to misbehave. Ensure to > > > > Do you means SCL have additional toggle? You capture waveform? > > > > Yes exactly. We were able to capture the waveform when the issue > happens. It doesn't always happen though, it depends on how much time > passes between clearing MSTA and MTX and reading from I2DR. > > If you want to see the waveform, I uploaded it to our server: > https://share.toradex.com/dwnhcrl6b9toib6 > You can see the additional clock at the right end, after "0x17 + NAK". Have you had a chance to look at the waveform? Do you have any concerns about the proposed solution? Best regards, Stefan