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Wed, 04 Mar 2026 20:19:22 -0800 (PST) Received: from geday ([2804:7f2:8080:fd2e::1]) by smtp.gmail.com with ESMTPSA id a1e0cc1a2514c-94df6577a4fsm21273560241.10.2026.03.04.20.19.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Mar 2026 20:19:21 -0800 (PST) Date: Thu, 5 Mar 2026 01:19:15 -0300 From: Geraldo Nascimento To: Dragan Simic Cc: Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-rockchip@lists.infradead.org, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v5 3/4] PCI: rockchip: drive at 2.5 GT/s, error other speeds Message-ID: References: <2a0a4aa97bb8b0cb511cb651c5d66c9ec8bab97a.1772239598.git.geraldogabriel@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260304_201924_279279_730CB262 X-CRM114-Status: GOOD ( 39.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Feb 28, 2026 at 07:16:41AM +0100, Dragan Simic wrote: > Hello Geraldo, Hi Dragan, > > On Saturday, February 28, 2026 01:55 CET, Geraldo Nascimento wrote: > > Configure the core to be driven at 2.5 GT/s Link Speed and ignore > > any other speed with a warning. The reason is that Shawn Lin from > > Rockchip has reiterated that there may be danger of "catastrophic > > failure" in using their PCIe with 5.0 GT/s speeds. > > > > While Rockchip has done so informally without issuing a proper errata, > > and the particulars are thus unknown, this may cause data loss or > > worse. > > > > This change is corroborated by RK3399 official datasheet [1], which > > states maximum link speed for this platform is 2.5 GT/s. > > > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf > > > > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") > > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ > > Cc: stable@vger.kernel.org > > Reported-by: Dragan Simic > > Reported-by: Shawn Lin > > Signed-off-by: Geraldo Nascimento > > --- > > drivers/pci/controller/pcie-rockchip.c | 15 +++++++++------ > > 1 file changed, 9 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > > index 0f88da378805..2f211d1f4c7c 100644 > > --- a/drivers/pci/controller/pcie-rockchip.c > > +++ b/drivers/pci/controller/pcie-rockchip.c > > @@ -66,8 +66,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > > } > > > > rockchip->link_gen = of_pci_get_max_link_speed(node); > > - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) > > - rockchip->link_gen = 2; > > + if (rockchip->link_gen < 0 || rockchip->link_gen >= 2) { > > + rockchip->link_gen = 1; > > + dev_warn(dev, "invalid max-link-speed, fix your DT\n"); > > + } > > I'd suggest using a bit more formal message here, like the one below, > which would also avoid addressing the user directly: > > "Invalid max-link-speed found, limited to Gen1 to avoid data corruption" We really should spare on characters here, but I see your point and will try to cook up a better way. > > > for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) > > rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; > > @@ -147,12 +149,13 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > > goto err_exit_phy; > > } > > > > - if (rockchip->link_gen == 2) > > - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, > > - PCIE_CLIENT_CONFIG); > > - else > > + if (rockchip->link_gen == 2) { > > + /* 5.0 GT/s may cause catastrophic failure for this core */ > > + dev_warn(dev, "5.0 GT/s may cause data loss or worse\n"); > > + } else { > > rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, > > PCIE_CLIENT_CONFIG); > > + } > > I don't think we need to emit a warning here, because, as we've already > established through earlier discussions, the rockchip_pcie_init_port() > function should never receive an invalid speed value. Just as a lame excuse, those messages were everywhere in the mid of my development, this is one that escaped deletion, will drop. > > > regs = PCIE_CLIENT_ARI_ENABLE | > > PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); > > It would make most sense to squash all three patches in this series > into a single patch, because they all form a single logical unit, which > introduces changes that are just going to be harder to track down later > if it's all scattered into multiple separate patches. I agree, having all drops in one big patch is the better tactic here. > > The only possible issue with the squashing comes from the inability to > have different patch subject prefixes for different driver changes, but > I think that's actually not an issue. The long-term benefits of having > everything as a single patch outweighs the benefits of having different > patch subjects with separate patches. > Sure, will do so for v6. Many thanks, Geraldo Nascimento