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[34.83.136.168]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ae840b2130sm30703795ad.83.2026.03.06.11.59.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Mar 2026 11:59:37 -0800 (PST) Date: Fri, 6 Mar 2026 19:59:33 +0000 From: Samiullah Khawaja To: Jason Gunthorpe Cc: Baolu Lu , Nicolin Chen , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, bhelgaas@google.com, rafael@kernel.org, lenb@kernel.org, praan@google.com, kees@kernel.org, smostafa@google.com, Alexander.Grest@microsoft.com, kevin.tian@intel.com, miko.lenczewski@arm.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, vsethi@nvidia.com Subject: Re: [PATCH v1 2/2] iommu/arm-smmu-v3: Recover ATC invalidate timeouts Message-ID: References: <20260305153911.GT972761@nvidia.com> <6416b7fe-0190-4c7b-9a62-5da7d5eea794@linux.intel.com> <20260306130006.GF1651202@nvidia.com> <20260306194312.GL1651202@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20260306194312.GL1651202@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260306_115939_476713_9E6F6880 X-CRM114-Status: GOOD ( 22.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Mar 06, 2026 at 03:43:12PM -0400, Jason Gunthorpe wrote: >On Fri, Mar 06, 2026 at 07:35:19PM +0000, Samiullah Khawaja wrote: >> On Fri, Mar 06, 2026 at 09:00:06AM -0400, Jason Gunthorpe wrote: >> > On Fri, Mar 06, 2026 at 11:22:52AM +0800, Baolu Lu wrote: >> > > I believe this issue is not unique to the arm-smmu-v3 driver. Device ATC >> > > invalidation timeout is a generic challenge across all IOMMU >> > > architectures that support PCI ATS. Would it be feasible to implement a >> > > common 'fencing and recovery' mechanism in the IOMMU core so that all >> > > IOMMU drivers could benefit? >> > >> > I think yes, for parts, but the driver itself has to do something deep >> > inside it's invalidation to allow the flush to complete without >> > exposing the system to memory corruption - meaning it has to block >> > translated requests before completing the flush >> >> Yes and currently the underlying drivers have software timeouts >> (AMD=100millisecond, arm-smmu-v3=1second) defined which could timeout >> before the actual ATC invalidation timeout occurs. Do you think maybe >> the timeout needs to be propagated to the caller (flush callback) so the >> memory/IOVA is not allocated to something else? > >No, definitely not, that's basically impossible, so many callers just >can't handle such an idea, and you can't ever fully recover from such >a thing. > Agreed. >> Or blocking translated requests for such devices should be enough? > >Yes, we have to fence the hardware and then allow the existing SW >stack to continue without any fear of UAF from the broken HW. And this applies to software timeout also I think, since both have same end result. I am working on a series to solve this for VT-d and testing it internally. > >Fencing the HW means using the IOMMU to block translated requests. > >Jason