[PATCH v5 0/7] Add PCIe, SERDES and USB DT support for J722S

[PATCH v5 0/7] Add PCIe, SERDES and USB DT support for J722S

[Siddharth Vadapalli]

Hello,

This series adds the device-tree support for enabling PCIe and USB
functionality on J722S-EVM.

Since AM62P and J722S SoCs share most of the peripherals, the files have
been renamed to indicate the same. The main domain peripherals on both
SoCs that aren't shared are present in the "soc-main.dtsi" files.
This change has been made based on Roger's feedback at:
https://lore.kernel.org/r/f52d9569-a399-422f-9cf0-b0bf69b64d18@kernel.org/

This series has been tested on J722S-EVM for PCIe and USB functionality:
https://gist.github.com/Siddharth-Vadapalli-at-TI/02c037efd3666ea8232d7bb8b0fa42f3

Sanity testing on AM62P5-SK with this series:
https://gist.github.com/Siddharth-Vadapalli-at-TI/1fb178f31b7cbc8eefd424e1e540ef3b

v4:
https://lore.kernel.org/r/20240601121554.2860403-1-s-vadapalli@ti.com/
Changes since v4:
- Rebased series on linux-next tagged next-20240604.
- Based on Andrew's feedback at:
  https://lore.kernel.org/r/086fa11e-10f8-463d-8966-1a33a52a3146@ti.com/
  MCU was retained as-is while main and wakeup were changed to MAIN and
  WAKEUP in the respective shared files. Also, newline was added between
  the file description and the Copyright in all the files.
  Collected Acked-by tag for the 1st patch since these changes have been
  made.
- Based on Andrew's feedback at:
  https://lore.kernel.org/r/147d58a6-0cad-47b6-a069-755f835a77e9@ti.com/
  SERDES1 has also been disabled in k3-j722s-main.dtsi similar to SERDES0.
- Based on Andrew's feedback at:
  https://lore.kernel.org/r/183a9d15-939e-433b-84ba-8a64eb8ef3ec@ti.com/
  the `status = "okay";` line has been moved to the end of the
  `pcie0_rc` node referenced in k3-j722s-evm.dts following the updated
  ordering rules. Also, the SERDES1 node has been enabled in the
  k3-j722s-evm.dts file since it has been disabled in the
  k3-j722s-main.dtsi file.

Regards,
Siddharth.

Siddharth Vadapalli (7):
  arm64: dts: ti: am62p: Rename am62p-{}.dtsi to
    am62p-j722s-common-{}.dtsi
  arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to
    am62p-main.dtsi
  arm64: dts: ti: k3-j722s: Add main domain peripherals specific to
    J722S
  arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi
  arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for
    J722S
  arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support
  arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM

 .../dts/ti/k3-am62p-j722s-common-main.dtsi    | 1068 +++++++++++++++++
 ...cu.dtsi => k3-am62p-j722s-common-mcu.dtsi} |    3 +-
 ...dtsi => k3-am62p-j722s-common-wakeup.dtsi} |    3 +-
 ...-am62p.dtsi => k3-am62p-j722s-common.dtsi} |    6 +-
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 1063 +---------------
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi         |    3 +-
 arch/arm64/boot/dts/ti/k3-j722s-evm.dts       |   73 ++
 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi     |  173 +++
 arch/arm64/boot/dts/ti/k3-j722s.dtsi          |   97 +-
 arch/arm64/boot/dts/ti/k3-serdes.h            |    8 +
 10 files changed, 1429 insertions(+), 1068 deletions(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
 rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
 rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
 rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

-- 
2.40.1


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[PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Siddharth Vadapalli]

The AM62P and J722S SoCs share most of the peripherals. With the aim of
reusing the existing k3-am62p-{mcu,main,wakeup}.dtsi files for J722S SoC,
rename them to indicate that they are shared with J722S SoC.

The peripherals that are not shared will be moved in the upcoming patches
to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in
the filename, emphasizing that they are not shared.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-2-s-vadapalli@ti.com/
Changes since v4:
- Based on Andrew's feedback at:
  https://lore.kernel.org/r/086fa11e-10f8-463d-8966-1a33a52a3146@ti.com/
  MCU was retained as-is while main and wakeup were changed to MAIN and
  WAKEUP in the respective shared files.
- Newline has been added between the file description and the Copyright
  in all the files.
- Collected Acked-by tag since these changes have been made.

 .../{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} | 3 ++-
 .../{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi}   | 3 ++-
 ...-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} | 3 ++-
 .../dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi}    | 6 +++---
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi                       | 2 +-
 5 files changed, 10 insertions(+), 7 deletions(-)
 rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} (99%)
 rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
 rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
 rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%)

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
similarity index 99%
rename from arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index 900d1f9530a2..bf6384ba824a 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 /*
- * Device Tree file for the AM62P main domain peripherals
+ * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S
+ *
  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
similarity index 98%
rename from arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
index b973b550eb9d..1d4e5fc8b4e0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 /*
- * Device Tree file for the AM62P MCU domain peripherals
+ * Device Tree file for the MCU domain peripherals shared by AM62P and J722S
+ *
  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
index c71d9624ea27..f6ec6e8e171d 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only OR MIT
 /*
- * Device Tree file for the AM62P wakeup domain peripherals
+ * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
+ *
  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/ti/k3-am62p.dtsi
rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common.dtsi
index 94babc412575..d85d05e0792a 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common.dtsi
@@ -120,6 +120,6 @@ cbass_wakeup: bus@b00000 {
 };
 
 /* Now include peripherals for each bus segment */
-#include "k3-am62p-main.dtsi"
-#include "k3-am62p-mcu.dtsi"
-#include "k3-am62p-wakeup.dtsi"
+#include "k3-am62p-j722s-common-main.dtsi"
+#include "k3-am62p-j722s-common-mcu.dtsi"
+#include "k3-am62p-j722s-common-wakeup.dtsi"
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
index 41f479dca455..b7bb04a7968f 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
@@ -8,7 +8,7 @@
 
 /dts-v1/;
 
-#include "k3-am62p.dtsi"
+#include "k3-am62p-j722s-common.dtsi"
 
 / {
 	cpus {
-- 
2.40.1


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Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Roger Quadros]

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> The AM62P and J722S SoCs share most of the peripherals. With the aim of
> reusing the existing k3-am62p-{mcu,main,wakeup}.dtsi files for J722S SoC,
> rename them to indicate that they are shared with J722S SoC.
> 
> The peripherals that are not shared will be moved in the upcoming patches
> to the respective k3-{soc}-{mcu,main,wakeup}.dtsi files without "common" in
> the filename, emphasizing that they are not shared.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> Acked-by: Andrew Davis <afd@ti.com>
> ---
> v4:
> https://lore.kernel.org/r/20240601121554.2860403-2-s-vadapalli@ti.com/
> Changes since v4:
> - Based on Andrew's feedback at:
>   https://lore.kernel.org/r/086fa11e-10f8-463d-8966-1a33a52a3146@ti.com/
>   MCU was retained as-is while main and wakeup were changed to MAIN and
>   WAKEUP in the respective shared files.
> - Newline has been added between the file description and the Copyright
>   in all the files.
> - Collected Acked-by tag since these changes have been made.
> 
>  .../{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} | 3 ++-
>  .../{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi}   | 3 ++-
>  ...-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} | 3 ++-
>  .../dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi}    | 6 +++---
>  arch/arm64/boot/dts/ti/k3-am62p5.dtsi                       | 2 +-
>  5 files changed, 10 insertions(+), 7 deletions(-)
>  rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} (99%)
>  rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
>  rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
>  rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%)

This is not correct.
If J722 has different CBASS components than AM62p then we should leave k3-am62p.dtsi
as it is and introduce a new k3-j722.dtsi with relevant CBASS components.

> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> similarity index 99%
> rename from arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> index 900d1f9530a2..bf6384ba824a 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-only OR MIT
>  /*
> - * Device Tree file for the AM62P main domain peripherals
> + * Device Tree file for the MAIN domain peripherals shared by AM62P and J722S
> + *
>   * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
> similarity index 98%
> rename from arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
> rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
> index b973b550eb9d..1d4e5fc8b4e0 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-mcu.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-only OR MIT
>  /*
> - * Device Tree file for the AM62P MCU domain peripherals
> + * Device Tree file for the MCU domain peripherals shared by AM62P and J722S
> + *
>   * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> similarity index 97%
> rename from arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
> rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> index c71d9624ea27..f6ec6e8e171d 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-wakeup.dtsi
> @@ -1,6 +1,7 @@
>  // SPDX-License-Identifier: GPL-2.0-only OR MIT
>  /*
> - * Device Tree file for the AM62P wakeup domain peripherals
> + * Device Tree file for the WAKEUP domain peripherals shared by AM62P and J722S
> + *
>   * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
>   */
>  
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common.dtsi
> similarity index 97%
> rename from arch/arm64/boot/dts/ti/k3-am62p.dtsi
> rename to arch/arm64/boot/dts/ti/k3-am62p-j722s-common.dtsi
> index 94babc412575..d85d05e0792a 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common.dtsi
> @@ -120,6 +120,6 @@ cbass_wakeup: bus@b00000 {
>  };
>  
>  /* Now include peripherals for each bus segment */
> -#include "k3-am62p-main.dtsi"
> -#include "k3-am62p-mcu.dtsi"
> -#include "k3-am62p-wakeup.dtsi"
> +#include "k3-am62p-j722s-common-main.dtsi"
> +#include "k3-am62p-j722s-common-mcu.dtsi"
> +#include "k3-am62p-j722s-common-wakeup.dtsi"
> diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> index 41f479dca455..b7bb04a7968f 100644
> --- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
> @@ -8,7 +8,7 @@
>  
>  /dts-v1/;
>  
> -#include "k3-am62p.dtsi"
> +#include "k3-am62p-j722s-common.dtsi"
>  
>  / {
>  	cpus {

--
cheers,
-roger

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Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Siddharth Vadapalli]

On Thu, Jun 06, 2024 at 10:51:27AM +0300, Roger Quadros wrote:

[...]

> >  5 files changed, 10 insertions(+), 7 deletions(-)
> >  rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} (99%)
> >  rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
> >  rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
> >  rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%)
> 
> This is not correct.
> If J722 has different CBASS components than AM62p then we should leave k3-am62p.dtsi
> as it is and introduce a new k3-j722.dtsi with relevant CBASS components.

Roger,

The existing hierarchy prior to this series is as follows:
k3-am62p.dtsi = k3-am62p-main.dtsi + k3-am62p-mcu.dtsi +
		k3-am62p-wakeup.dtsi + k3-am62p-thermal.dtsi + <delta-1>
k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
k3-j722s.dtsi = k3-am62p5.dtsi + <delta-3>
k3-j722s-evm.dts = k3-j722s.dtsi + <detla-4>

Based on your suggestion, you seem to propose the following hierarchy:
k3-am62p-{main,mcu,thermal,wakeup}.dtsi = AM62P specific data
k3-am62p.dtsi = k3-am62p-j722s-common-main.dtsi +
		k3-am62p-j722s-common-mcu.dtsi +
		k3-am62p-j722s-common-wakeup.dtsi +
		k3-am62p-j722s-common-thermal.dtsi +
		k3-am62p-{main,mcu,thermal,wakeup}.dtsi +
		<delta-5>
k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
k3-j722s-{main,mcu,thermal,wakeup}.dtsi = J722S specific data
k3-j722s.dtsi = k3-am62p-j722s-common-main.dtsi +
		k3-am62p-j722s-common-mcu.dtsi +
		k3-am62p-j722s-common-wakeup.dtsi +
		k3-am62p-j722s-common-thermal.dtsi +
		k3-j722s-{main,mcu,thermal,wakeup}.dtsi +
		<delta-6>
k3-j722s-evm.dts = k3-j722s.dtsi + <delta-4>

Please let me know whether the above organization of files matches what you
expect it to look like. I will post the v6 series based on your feedback.

Regards,
Siddharth.

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Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Roger Quadros]

Siddharth,

On 07/06/2024 14:28, Siddharth Vadapalli wrote:
> On Thu, Jun 06, 2024 at 10:51:27AM +0300, Roger Quadros wrote:
> 
> [...]
> 
>>>  5 files changed, 10 insertions(+), 7 deletions(-)
>>>  rename arch/arm64/boot/dts/ti/{k3-am62p-main.dtsi => k3-am62p-j722s-common-main.dtsi} (99%)
>>>  rename arch/arm64/boot/dts/ti/{k3-am62p-mcu.dtsi => k3-am62p-j722s-common-mcu.dtsi} (98%)
>>>  rename arch/arm64/boot/dts/ti/{k3-am62p-wakeup.dtsi => k3-am62p-j722s-common-wakeup.dtsi} (97%)
>>>  rename arch/arm64/boot/dts/ti/{k3-am62p.dtsi => k3-am62p-j722s-common.dtsi} (97%)
>>
>> This is not correct.
>> If J722 has different CBASS components than AM62p then we should leave k3-am62p.dtsi
>> as it is and introduce a new k3-j722.dtsi with relevant CBASS components.
> 
> Roger,
> 
> The existing hierarchy prior to this series is as follows:
> k3-am62p.dtsi = k3-am62p-main.dtsi + k3-am62p-mcu.dtsi +
> 		k3-am62p-wakeup.dtsi + k3-am62p-thermal.dtsi + <delta-1>
> k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
> k3-j722s.dtsi = k3-am62p5.dtsi + <delta-3>
> k3-j722s-evm.dts = k3-j722s.dtsi + <detla-4>
> 
> Based on your suggestion, you seem to propose the following hierarchy:
> k3-am62p-{main,mcu,thermal,wakeup}.dtsi = AM62P specific data
> k3-am62p.dtsi = k3-am62p-j722s-common-main.dtsi +
> 		k3-am62p-j722s-common-mcu.dtsi +
> 		k3-am62p-j722s-common-wakeup.dtsi +
> 		k3-am62p-j722s-common-thermal.dtsi +
> 		k3-am62p-{main,mcu,thermal,wakeup}.dtsi +
> 		<delta-5>
> k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
> k3-j722s-{main,mcu,thermal,wakeup}.dtsi = J722S specific data
> k3-j722s.dtsi = k3-am62p-j722s-common-main.dtsi +
> 		k3-am62p-j722s-common-mcu.dtsi +
> 		k3-am62p-j722s-common-wakeup.dtsi +
> 		k3-am62p-j722s-common-thermal.dtsi +
> 		k3-j722s-{main,mcu,thermal,wakeup}.dtsi +
> 		<delta-6>

What is the equivalent of k3-am62p5.dtsi here?
That should contain k3-j722s.dtsi + CPU and OPP stuff.

I suppose it should be named specific to the SoC variant part number?

> k3-j722s-evm.dts = k3-j722s.dtsi + <delta-4>
> 
> Please let me know whether the above organization of files matches what you
> expect it to look like. I will post the v6 series based on your feedback.
> 
> Regards,
> Siddharth.

-- 
cheers,
-roger

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Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Siddharth Vadapalli]

On Mon, Jun 10, 2024 at 10:31:07PM +0300, Roger Quadros wrote:

[...]

> > Based on your suggestion, you seem to propose the following hierarchy:
> > k3-am62p-{main,mcu,thermal,wakeup}.dtsi = AM62P specific data
> > k3-am62p.dtsi = k3-am62p-j722s-common-main.dtsi +
> > 		k3-am62p-j722s-common-mcu.dtsi +
> > 		k3-am62p-j722s-common-wakeup.dtsi +
> > 		k3-am62p-j722s-common-thermal.dtsi +
> > 		k3-am62p-{main,mcu,thermal,wakeup}.dtsi +
> > 		<delta-5>
> > k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
> > k3-j722s-{main,mcu,thermal,wakeup}.dtsi = J722S specific data
> > k3-j722s.dtsi = k3-am62p-j722s-common-main.dtsi +
> > 		k3-am62p-j722s-common-mcu.dtsi +
> > 		k3-am62p-j722s-common-wakeup.dtsi +
> > 		k3-am62p-j722s-common-thermal.dtsi +
> > 		k3-j722s-{main,mcu,thermal,wakeup}.dtsi +
> > 		<delta-6>
> 
> What is the equivalent of k3-am62p5.dtsi here?
> That should contain k3-j722s.dtsi + CPU and OPP stuff.
> 
> I suppose it should be named specific to the SoC variant part number?

AM62P (https://www.ti.com/product/AM62P) has two variants:
1. 2 Arm Cortex-A53 => AM62P3
2. 4 Arm Cortex-A53 => AM62P5
Both variants will share the common k3-am62p.dtsi

J722S (https://www.ti.com/product/TDA4VEN-Q1) has only one variant:
4 Arm Cortex-A53 => J722S
Which is currently identical to AM62P5 w.r.t. the number of A53s.

So there isn't an equivalent of AM62P5/k3-am62p5.dtsi for J722S.
k3-j722s.dtsi is a combination of k3-am62p.dtsi and k3-am62p5.dtsi.

Regards,
Siddharth.

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Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Vignesh Raghavendra]

On 11/06/24 14:24, Siddharth Vadapalli wrote:
> On Mon, Jun 10, 2024 at 10:31:07PM +0300, Roger Quadros wrote:
> 
> [...]
> 
>>> Based on your suggestion, you seem to propose the following hierarchy:
>>> k3-am62p-{main,mcu,thermal,wakeup}.dtsi = AM62P specific data
>>> k3-am62p.dtsi = k3-am62p-j722s-common-main.dtsi +
>>> 		k3-am62p-j722s-common-mcu.dtsi +
>>> 		k3-am62p-j722s-common-wakeup.dtsi +
>>> 		k3-am62p-j722s-common-thermal.dtsi +
>>> 		k3-am62p-{main,mcu,thermal,wakeup}.dtsi +
>>> 		<delta-5>
>>> k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
>>> k3-j722s-{main,mcu,thermal,wakeup}.dtsi = J722S specific data
>>> k3-j722s.dtsi = k3-am62p-j722s-common-main.dtsi +
>>> 		k3-am62p-j722s-common-mcu.dtsi +
>>> 		k3-am62p-j722s-common-wakeup.dtsi +
>>> 		k3-am62p-j722s-common-thermal.dtsi +
>>> 		k3-j722s-{main,mcu,thermal,wakeup}.dtsi +
>>> 		<delta-6>
>>
>> What is the equivalent of k3-am62p5.dtsi here?
>> That should contain k3-j722s.dtsi + CPU and OPP stuff.
>>
>> I suppose it should be named specific to the SoC variant part number?
> 
> AM62P (https://www.ti.com/product/AM62P) has two variants:
> 1. 2 Arm Cortex-A53 => AM62P3
> 2. 4 Arm Cortex-A53 => AM62P5
> Both variants will share the common k3-am62p.dtsi
> 
> J722S (https://www.ti.com/product/TDA4VEN-Q1) has only one variant:
> 4 Arm Cortex-A53 => J722S
> Which is currently identical to AM62P5 w.r.t. the number of A53s.
> 
> So there isn't an equivalent of AM62P5/k3-am62p5.dtsi for J722S.
> k3-j722s.dtsi is a combination of k3-am62p.dtsi and k3-am62p5.dtsi.
> 


Historically AM6xx devices have had CPUs in separte file as there are OPNs with different number of CPU cores Hence, how about
k3-am62p5.dtsi => k3-am62p.dtsi + k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-am62p-main.dtsi (USB2 and other deltas specific to AM62P)

and since J722s has no variants with less than 4 cores (and along the lines of rest of J7xx devices):

k3-j722s.dtsi => k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-j722s-main.dtsi (USB3, C7x and other deltas specific to J722s;


-- 
Regards
Vignesh

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Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Roger Quadros]

On 11/06/2024 12:10, Vignesh Raghavendra wrote:
> 
> 
> On 11/06/24 14:24, Siddharth Vadapalli wrote:
>> On Mon, Jun 10, 2024 at 10:31:07PM +0300, Roger Quadros wrote:
>>
>> [...]
>>
>>>> Based on your suggestion, you seem to propose the following hierarchy:
>>>> k3-am62p-{main,mcu,thermal,wakeup}.dtsi = AM62P specific data
>>>> k3-am62p.dtsi = k3-am62p-j722s-common-main.dtsi +
>>>> 		k3-am62p-j722s-common-mcu.dtsi +
>>>> 		k3-am62p-j722s-common-wakeup.dtsi +
>>>> 		k3-am62p-j722s-common-thermal.dtsi +
>>>> 		k3-am62p-{main,mcu,thermal,wakeup}.dtsi +
>>>> 		<delta-5>
>>>> k3-am62p5.dtsi = k3-am62p.dtsi + <delta-2>
>>>> k3-j722s-{main,mcu,thermal,wakeup}.dtsi = J722S specific data
>>>> k3-j722s.dtsi = k3-am62p-j722s-common-main.dtsi +
>>>> 		k3-am62p-j722s-common-mcu.dtsi +
>>>> 		k3-am62p-j722s-common-wakeup.dtsi +
>>>> 		k3-am62p-j722s-common-thermal.dtsi +
>>>> 		k3-j722s-{main,mcu,thermal,wakeup}.dtsi +
>>>> 		<delta-6>
>>>
>>> What is the equivalent of k3-am62p5.dtsi here?
>>> That should contain k3-j722s.dtsi + CPU and OPP stuff.
>>>
>>> I suppose it should be named specific to the SoC variant part number?
>>
>> AM62P (https://www.ti.com/product/AM62P) has two variants:
>> 1. 2 Arm Cortex-A53 => AM62P3
>> 2. 4 Arm Cortex-A53 => AM62P5
>> Both variants will share the common k3-am62p.dtsi
>>
>> J722S (https://www.ti.com/product/TDA4VEN-Q1) has only one variant:
>> 4 Arm Cortex-A53 => J722S
>> Which is currently identical to AM62P5 w.r.t. the number of A53s.
>>
>> So there isn't an equivalent of AM62P5/k3-am62p5.dtsi for J722S.
>> k3-j722s.dtsi is a combination of k3-am62p.dtsi and k3-am62p5.dtsi.
>>
> 
> 
> Historically AM6xx devices have had CPUs in separte file as there are OPNs with different number of CPU cores Hence, how about
> k3-am62p5.dtsi => k3-am62p.dtsi + k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-am62p-main.dtsi (USB2 and other deltas specific to AM62P)
> 
> and since J722s has no variants with less than 4 cores (and along the lines of rest of J7xx devices):
> 
> k3-j722s.dtsi => k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-j722s-main.dtsi (USB3, C7x and other deltas specific to J722s;
> 
> 

Seems OK to me.

-- 
cheers,
-roger

Re: [PATCH v5 1/7] arm64: dts: ti: am62p: Rename am62p-{}.dtsi to am62p-j722s-common-{}.dtsi

[Siddharth Vadapalli]

On Tue, Jun 11, 2024 at 08:18:34PM +0300, Roger Quadros wrote:
> 
> 
> On 11/06/2024 12:10, Vignesh Raghavendra wrote:
> > 
> > 
> > On 11/06/24 14:24, Siddharth Vadapalli wrote:
> >> On Mon, Jun 10, 2024 at 10:31:07PM +0300, Roger Quadros wrote:

[...]

> >>>
> >>> What is the equivalent of k3-am62p5.dtsi here?
> >>> That should contain k3-j722s.dtsi + CPU and OPP stuff.
> >>>
> >>> I suppose it should be named specific to the SoC variant part number?
> >>
> >> AM62P (https://www.ti.com/product/AM62P) has two variants:
> >> 1. 2 Arm Cortex-A53 => AM62P3
> >> 2. 4 Arm Cortex-A53 => AM62P5
> >> Both variants will share the common k3-am62p.dtsi
> >>
> >> J722S (https://www.ti.com/product/TDA4VEN-Q1) has only one variant:
> >> 4 Arm Cortex-A53 => J722S
> >> Which is currently identical to AM62P5 w.r.t. the number of A53s.
> >>
> >> So there isn't an equivalent of AM62P5/k3-am62p5.dtsi for J722S.
> >> k3-j722s.dtsi is a combination of k3-am62p.dtsi and k3-am62p5.dtsi.
> >>
> > 
> > 
> > Historically AM6xx devices have had CPUs in separte file as there are OPNs with different number of CPU cores Hence, how about
> > k3-am62p5.dtsi => k3-am62p.dtsi + k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-am62p-main.dtsi (USB2 and other deltas specific to AM62P)
> > 
> > and since J722s has no variants with less than 4 cores (and along the lines of rest of J7xx devices):
> > 
> > k3-j722s.dtsi => k3-am62p-j722s-common-{main,mcu,wakeup}.dtsi + k3-j722s-main.dtsi (USB3, C7x and other deltas specific to J722s;
> > 
> > 
> 
> Seems OK to me.

Vignesh, Roger,

I will implement the above in the v6 series.

Regards,
Siddharth.

[PATCH v5 2/7] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi

[Siddharth Vadapalli]

The USB1 instance of USB controller on AM62P is different from the USB1
instance of USB controller on J722S. Thus, move the USB1 instance from
the shared "k3-am62p-j722s-common-main.dtsi" file to the AM62p specific
"k3-am62p-main.dtsi" file.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-3-s-vadapalli@ti.com/
Changes since v4:
- s/main/MAIN in k3-am62p-main.dtsi

 .../dts/ti/k3-am62p-j722s-common-main.dtsi    | 26 --------------
 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi     | 34 +++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am62p5.dtsi         |  1 +
 3 files changed, 35 insertions(+), 26 deletions(-)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62p-main.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index bf6384ba824a..80d2e559a473 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -662,32 +662,6 @@ usb0: usb@31000000 {
 		};
 	};
 
-	usbss1: usb@f910000 {
-		compatible = "ti,am62-usb";
-		reg = <0x00 0x0f910000 0x00 0x800>,
-		      <0x00 0x0f918000 0x00 0x400>;
-		clocks = <&k3_clks 162 3>;
-		clock-names = "ref";
-		ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
-		#address-cells = <2>;
-		#size-cells = <2>;
-		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
-		ranges;
-		status = "disabled";
-
-		usb1: usb@31100000 {
-			compatible = "snps,dwc3";
-			reg = <0x00 0x31100000 0x00 0x50000>;
-			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
-			<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
-			interrupt-names = "host", "peripheral";
-			maximum-speed = "high-speed";
-			dr_mode = "otg";
-			snps,usb2-gadget-lpm-disable;
-			snps,usb2-lpm-disable;
-		};
-	};
-
 	fss: bus@fc00000 {
 		compatible = "simple-bus";
 		reg = <0x00 0x0fc00000 0x00 0x70000>;
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
new file mode 100644
index 000000000000..9caab7db5440
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62p-main.dtsi
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the AM62P MAIN domain peripherals
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+	usbss1: usb@f910000 {
+		compatible = "ti,am62-usb";
+		reg = <0x00 0x0f910000 0x00 0x800>,
+		      <0x00 0x0f918000 0x00 0x400>;
+		clocks = <&k3_clks 162 3>;
+		clock-names = "ref";
+		ti,syscon-phy-pll-refclk = <&usb1_phy_ctrl 0x0>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
+		ranges;
+		status = "disabled";
+
+		usb1: usb@31100000 {
+			compatible = "snps,dwc3";
+			reg = <0x00 0x31100000 0x00 0x50000>;
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+			<GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; /* irq.0 */
+			interrupt-names = "host", "peripheral";
+			maximum-speed = "high-speed";
+			dr_mode = "otg";
+			snps,usb2-gadget-lpm-disable;
+			snps,usb2-lpm-disable;
+		};
+	};
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
index b7bb04a7968f..9f5bd76bf050 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p5.dtsi
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 #include "k3-am62p-j722s-common.dtsi"
+#include "k3-am62p-main.dtsi"
 
 / {
 	cpus {
-- 
2.40.1


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Re: [PATCH v5 2/7] arm64: dts: ti: k3-am62p-j722s: Move AM62P specific USB1 to am62p-main.dtsi

[Roger Quadros]

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> The USB1 instance of USB controller on AM62P is different from the USB1
> instance of USB controller on J722S. Thus, move the USB1 instance from
> the shared "k3-am62p-j722s-common-main.dtsi" file to the AM62p specific
> "k3-am62p-main.dtsi" file.
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Acked-by: Roger Quadros <rogerq@kernel.org>

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[PATCH v5 3/7] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S

[Siddharth Vadapalli]

Introduce the "k3-j722s-main.dtsi" file to contain main domain peripherals
that are specific to J722S SoC and are not shared with AM62P. The USB1
instance of the USB controller on J722S is different from that on AM62P.
Thus, add the USB1 node in "k3-j722s-main.dtsi".

Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-4-s-vadapalli@ti.com/
Changes since v4:
- s/main/MAIN in k3-j722s-main.dtsi

 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 40 +++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
new file mode 100644
index 000000000000..84378fc839d6
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-only OR MIT
+/*
+ * Device Tree file for the J722S MAIN domain peripherals
+ *
+ * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+&cbass_main {
+	usbss1: usb@f920000 {
+		compatible = "ti,j721e-usb";
+		reg = <0x00 0x0f920000 0x00 0x100>;
+		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 278 3>, <&k3_clks 278 1>;
+		clock-names = "ref", "lpm";
+		assigned-clocks = <&k3_clks 278 3>; /* USB2_REFCLK */
+		assigned-clock-parents = <&k3_clks 278 4>; /* HF0SC0 */
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+
+		usb1: usb@31200000{
+			compatible = "cdns,usb3";
+			reg = <0x00 0x31200000 0x00 0x10000>,
+			      <0x00 0x31210000 0x00 0x10000>,
+			      <0x00 0x31220000 0x00 0x10000>;
+			reg-names = "otg",
+				    "xhci",
+				    "dev";
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
+				     <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, /* irq.6 */
+				     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; /* otgirq */
+			interrupt-names = "host",
+					  "peripheral",
+					  "otg";
+			maximum-speed = "super-speed";
+			dr_mode = "otg";
+		};
+	};
+};
-- 
2.40.1


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Re: [PATCH v5 3/7] arm64: dts: ti: k3-j722s: Add main domain peripherals specific to J722S

[Roger Quadros]

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> Introduce the "k3-j722s-main.dtsi" file to contain main domain peripherals
> that are specific to J722S SoC and are not shared with AM62P. The USB1
> instance of the USB controller on J722S is different from that on AM62P.
> Thus, add the USB1 node in "k3-j722s-main.dtsi".
> 
> Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Acked-by: Roger Quadros <rogerq@kernel.org>

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[PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi

[Siddharth Vadapalli]

Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which
contains the nodes shared with AM62P, followed by including the J722S
specific main domain peripherals contained in "k3-j722s-main.dtsi".

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-5-s-vadapalli@ti.com/
No changes since v4.

 arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++-
 1 file changed, 96 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
index c75744edb143..9e04e6a5c0fd 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
@@ -10,12 +10,107 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/soc/ti,sci_pm_domain.h>
 
-#include "k3-am62p5.dtsi"
+#include "k3-am62p-j722s-common.dtsi"
+#include "k3-j722s-main.dtsi"
 
 / {
 	model = "Texas Instruments K3 J722S SoC";
 	compatible = "ti,j722s";
 
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu-map {
+			cluster0: cluster0 {
+				core0 {
+					cpu = <&cpu0>;
+				};
+
+				core1 {
+					cpu = <&cpu1>;
+				};
+
+				core2 {
+					cpu = <&cpu2>;
+				};
+
+				core3 {
+					cpu = <&cpu3>;
+				};
+			};
+		};
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a53";
+			reg = <0x000>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 135 0>;
+		};
+
+		cpu1: cpu@1 {
+			compatible = "arm,cortex-a53";
+			reg = <0x001>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 136 0>;
+		};
+
+		cpu2: cpu@2 {
+			compatible = "arm,cortex-a53";
+			reg = <0x002>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 137 0>;
+		};
+
+		cpu3: cpu@3 {
+			compatible = "arm,cortex-a53";
+			reg = <0x003>;
+			device_type = "cpu";
+			enable-method = "psci";
+			i-cache-size = <0x8000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x8000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <128>;
+			next-level-cache = <&l2_0>;
+			clocks = <&k3_clks 138 0>;
+		};
+	};
+
+	l2_0: l2-cache0 {
+		compatible = "cache";
+		cache-unified;
+		cache-level = <2>;
+		cache-size = <0x80000>;
+		cache-line-size = <64>;
+		cache-sets = <512>;
+	};
+
 	cbass_main: bus@f0000 {
 		compatible = "simple-bus";
 		#address-cells = <2>;
-- 
2.40.1


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Re: [PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi

[Vignesh Raghavendra]

On 04/06/24 14:22, Siddharth Vadapalli wrote:
> Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which
> contains the nodes shared with AM62P, followed by including the J722S
> specific main domain peripherals contained in "k3-j722s-main.dtsi".
> 
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
> v4:
> https://lore.kernel.org/r/20240601121554.2860403-5-s-vadapalli@ti.com/
> No changes since v4.
> 
>  arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++-
>  1 file changed, 96 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> index c75744edb143..9e04e6a5c0fd 100644
> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
> @@ -10,12 +10,107 @@
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/soc/ti,sci_pm_domain.h>
>  
> -#include "k3-am62p5.dtsi"
> +#include "k3-am62p-j722s-common.dtsi"
> +#include "k3-j722s-main.dtsi"
>  
>  / {
>  	model = "Texas Instruments K3 J722S SoC";
>  	compatible = "ti,j722s";
>  
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		cpu-map {
> +			cluster0: cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +			};
> +		};
> +
> +		cpu0: cpu@0 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x000>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 135 0>;
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x001>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 136 0>;
> +		};
> +
> +		cpu2: cpu@2 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x002>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 137 0>;
> +		};
> +
> +		cpu3: cpu@3 {
> +			compatible = "arm,cortex-a53";
> +			reg = <0x003>;
> +			device_type = "cpu";
> +			enable-method = "psci";
> +			i-cache-size = <0x8000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x8000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <128>;
> +			next-level-cache = <&l2_0>;
> +			clocks = <&k3_clks 138 0>;
> +		};
> +	};
> +
> +	l2_0: l2-cache0 {
> +		compatible = "cache";
> +		cache-unified;
> +		cache-level = <2>;
> +		cache-size = <0x80000>;
> +		cache-line-size = <64>;
> +		cache-sets = <512>;
> +	};
> +
>  	cbass_main: bus@f0000 {
>  		compatible = "simple-bus";
>  		#address-cells = <2>;


You would need to move the rest of main domain overrides and cbass_main
definitions to k3-j722s-main.dtsi and limit this file to CPU definitions
similar to k3-am62p5.dtsi



-- 
Regards
Vignesh

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Re: [PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi

[Roger Quadros]

On 06/06/2024 07:05, Vignesh Raghavendra wrote:
> 
> 
> On 04/06/24 14:22, Siddharth Vadapalli wrote:
>> Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which
>> contains the nodes shared with AM62P, followed by including the J722S
>> specific main domain peripherals contained in "k3-j722s-main.dtsi".
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>> ---
>> v4:
>> https://lore.kernel.org/r/20240601121554.2860403-5-s-vadapalli@ti.com/
>> No changes since v4.
>>
>>  arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++-
>>  1 file changed, 96 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> index c75744edb143..9e04e6a5c0fd 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>> @@ -10,12 +10,107 @@
>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>  #include <dt-bindings/soc/ti,sci_pm_domain.h>
>>  
>> -#include "k3-am62p5.dtsi"
>> +#include "k3-am62p-j722s-common.dtsi"
>> +#include "k3-j722s-main.dtsi"
>>  
>>  / {
>>  	model = "Texas Instruments K3 J722S SoC";
>>  	compatible = "ti,j722s";
>>  
>> +	cpus {
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		cpu-map {
>> +			cluster0: cluster0 {
>> +				core0 {
>> +					cpu = <&cpu0>;
>> +				};
>> +
>> +				core1 {
>> +					cpu = <&cpu1>;
>> +				};
>> +
>> +				core2 {
>> +					cpu = <&cpu2>;
>> +				};
>> +
>> +				core3 {
>> +					cpu = <&cpu3>;
>> +				};
>> +			};
>> +		};
>> +
>> +		cpu0: cpu@0 {
>> +			compatible = "arm,cortex-a53";
>> +			reg = <0x000>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			i-cache-size = <0x8000>;
>> +			i-cache-line-size = <64>;
>> +			i-cache-sets = <256>;
>> +			d-cache-size = <0x8000>;
>> +			d-cache-line-size = <64>;
>> +			d-cache-sets = <128>;
>> +			next-level-cache = <&l2_0>;
>> +			clocks = <&k3_clks 135 0>;
>> +		};
>> +
>> +		cpu1: cpu@1 {
>> +			compatible = "arm,cortex-a53";
>> +			reg = <0x001>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			i-cache-size = <0x8000>;
>> +			i-cache-line-size = <64>;
>> +			i-cache-sets = <256>;
>> +			d-cache-size = <0x8000>;
>> +			d-cache-line-size = <64>;
>> +			d-cache-sets = <128>;
>> +			next-level-cache = <&l2_0>;
>> +			clocks = <&k3_clks 136 0>;
>> +		};
>> +
>> +		cpu2: cpu@2 {
>> +			compatible = "arm,cortex-a53";
>> +			reg = <0x002>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			i-cache-size = <0x8000>;
>> +			i-cache-line-size = <64>;
>> +			i-cache-sets = <256>;
>> +			d-cache-size = <0x8000>;
>> +			d-cache-line-size = <64>;
>> +			d-cache-sets = <128>;
>> +			next-level-cache = <&l2_0>;
>> +			clocks = <&k3_clks 137 0>;
>> +		};
>> +
>> +		cpu3: cpu@3 {
>> +			compatible = "arm,cortex-a53";
>> +			reg = <0x003>;
>> +			device_type = "cpu";
>> +			enable-method = "psci";
>> +			i-cache-size = <0x8000>;
>> +			i-cache-line-size = <64>;
>> +			i-cache-sets = <256>;
>> +			d-cache-size = <0x8000>;
>> +			d-cache-line-size = <64>;
>> +			d-cache-sets = <128>;
>> +			next-level-cache = <&l2_0>;
>> +			clocks = <&k3_clks 138 0>;
>> +		};
>> +	};
>> +
>> +	l2_0: l2-cache0 {
>> +		compatible = "cache";
>> +		cache-unified;
>> +		cache-level = <2>;
>> +		cache-size = <0x80000>;
>> +		cache-line-size = <64>;
>> +		cache-sets = <512>;
>> +	};
>> +
>>  	cbass_main: bus@f0000 {
>>  		compatible = "simple-bus";
>>  		#address-cells = <2>;
> 
> 
> You would need to move the rest of main domain overrides and cbass_main
> definitions to k3-j722s-main.dtsi and limit this file to CPU definitions
> similar to k3-am62p5.dtsi

Not exactly.
In existing cases there are 2 soc.dtsi files. e.g. k3-am62p.dtsi and k3-am62p5.dtsi.
or k3-am2.dtsi and k3-am625.dtsi.

The former includes everything that is required for the SOC variant except the CPU, OPP and cache.
The later includes just the CPU, OPP and cache.

I suppose this only makes sense if there are multiple variants of the SoC where only
the number of CPUs change. Would this be the case for J722S?

If not then one soc.dtsi file should be sufficient. If yes then we need to have 2 soc.dtsi files
for J722S like the rest.

-- 
cheers,
-roger

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Re: [PATCH v5 4/7] arm64: dts: ti: k3-j722s: Switch to k3-am62p-j722s-common.dtsi

[Vignesh Raghavendra]

On 06/06/24 13:04, Roger Quadros wrote:
> 
> 
> On 06/06/2024 07:05, Vignesh Raghavendra wrote:
>>
>>
>> On 04/06/24 14:22, Siddharth Vadapalli wrote:
>>> Update "k3-j722s.dtsi" to use "k3-am62p-j722s-common.dtsi" which
>>> contains the nodes shared with AM62P, followed by including the J722S
>>> specific main domain peripherals contained in "k3-j722s-main.dtsi".
>>>
>>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
>>> ---
>>> v4:
>>> https://lore.kernel.org/r/20240601121554.2860403-5-s-vadapalli@ti.com/
>>> No changes since v4.
>>>
>>>  arch/arm64/boot/dts/ti/k3-j722s.dtsi | 97 +++++++++++++++++++++++++++-
>>>  1 file changed, 96 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>> index c75744edb143..9e04e6a5c0fd 100644
>>> --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>> +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
>>> @@ -10,12 +10,107 @@
>>>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>>>  #include <dt-bindings/soc/ti,sci_pm_domain.h>
>>>  
>>> -#include "k3-am62p5.dtsi"
>>> +#include "k3-am62p-j722s-common.dtsi"
>>> +#include "k3-j722s-main.dtsi"
>>>  
>>>  / {
>>>  	model = "Texas Instruments K3 J722S SoC";
>>>  	compatible = "ti,j722s";
>>>  
>>> +	cpus {
>>> +		#address-cells = <1>;
>>> +		#size-cells = <0>;
>>> +
>>> +		cpu-map {
>>> +			cluster0: cluster0 {
>>> +				core0 {
>>> +					cpu = <&cpu0>;
>>> +				};
>>> +
>>> +				core1 {
>>> +					cpu = <&cpu1>;
>>> +				};
>>> +
>>> +				core2 {
>>> +					cpu = <&cpu2>;
>>> +				};
>>> +
>>> +				core3 {
>>> +					cpu = <&cpu3>;
>>> +				};
>>> +			};
>>> +		};
>>> +
>>> +		cpu0: cpu@0 {
>>> +			compatible = "arm,cortex-a53";
>>> +			reg = <0x000>;
>>> +			device_type = "cpu";
>>> +			enable-method = "psci";
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2_0>;
>>> +			clocks = <&k3_clks 135 0>;
>>> +		};
>>> +
>>> +		cpu1: cpu@1 {
>>> +			compatible = "arm,cortex-a53";
>>> +			reg = <0x001>;
>>> +			device_type = "cpu";
>>> +			enable-method = "psci";
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2_0>;
>>> +			clocks = <&k3_clks 136 0>;
>>> +		};
>>> +
>>> +		cpu2: cpu@2 {
>>> +			compatible = "arm,cortex-a53";
>>> +			reg = <0x002>;
>>> +			device_type = "cpu";
>>> +			enable-method = "psci";
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2_0>;
>>> +			clocks = <&k3_clks 137 0>;
>>> +		};
>>> +
>>> +		cpu3: cpu@3 {
>>> +			compatible = "arm,cortex-a53";
>>> +			reg = <0x003>;
>>> +			device_type = "cpu";
>>> +			enable-method = "psci";
>>> +			i-cache-size = <0x8000>;
>>> +			i-cache-line-size = <64>;
>>> +			i-cache-sets = <256>;
>>> +			d-cache-size = <0x8000>;
>>> +			d-cache-line-size = <64>;
>>> +			d-cache-sets = <128>;
>>> +			next-level-cache = <&l2_0>;
>>> +			clocks = <&k3_clks 138 0>;
>>> +		};
>>> +	};
>>> +
>>> +	l2_0: l2-cache0 {
>>> +		compatible = "cache";
>>> +		cache-unified;
>>> +		cache-level = <2>;
>>> +		cache-size = <0x80000>;
>>> +		cache-line-size = <64>;
>>> +		cache-sets = <512>;
>>> +	};
>>> +
>>>  	cbass_main: bus@f0000 {
>>>  		compatible = "simple-bus";
>>>  		#address-cells = <2>;
>>
>>
>> You would need to move the rest of main domain overrides and cbass_main
>> definitions to k3-j722s-main.dtsi and limit this file to CPU definitions
>> similar to k3-am62p5.dtsi
> 
> Not exactly.
> In existing cases there are 2 soc.dtsi files. e.g. k3-am62p.dtsi and k3-am62p5.dtsi.
> or k3-am2.dtsi and k3-am625.dtsi.
> 
> The former includes everything that is required for the SOC variant except the CPU, OPP and cache.
> The later includes just the CPU, OPP and cache.
> 
> I suppose this only makes sense if there are multiple variants of the SoC where only
> the number of CPUs change. Would this be the case for J722S?


Part numbers with different OPPs are expected besides difference in
number of cores for J722s.

> 
> If not then one soc.dtsi file should be sufficient. If yes then we need to have 2 soc.dtsi files
> for J722S like the rest.
> 

-- 
Regards
Vignesh

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[PATCH v5 5/7] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S

[Siddharth Vadapalli]

The SERDES0 and SERDES1 instances of SERDES on J722S are single lane
SERDES which are individually muxed across different peripherals.

LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is
muxed between PCIe and CPSW.

Define the lane-muxing macros to be used as the idle state values.

Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-6-s-vadapalli@ti.com/
No changes since v4.

 arch/arm64/boot/dts/ti/k3-serdes.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-serdes.h b/arch/arm64/boot/dts/ti/k3-serdes.h
index a011ad893b44..ef3606068140 100644
--- a/arch/arm64/boot/dts/ti/k3-serdes.h
+++ b/arch/arm64/boot/dts/ti/k3-serdes.h
@@ -201,4 +201,12 @@
 #define J784S4_SERDES4_LANE3_USB		0x2
 #define J784S4_SERDES4_LANE3_IP4_UNUSED		0x3
 
+/* J722S */
+
+#define J722S_SERDES0_LANE0_USB			0x0
+#define J722S_SERDES0_LANE0_QSGMII_LANE2	0x1
+
+#define J722S_SERDES1_LANE0_PCIE0_LANE0		0x0
+#define J722S_SERDES1_LANE0_QSGMII_LANE1	0x1
+
 #endif /* DTS_ARM64_TI_K3_SERDES_H */
-- 
2.40.1


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Re: [PATCH v5 5/7] arm64: dts: ti: k3-serdes: Add SERDES0/SERDES1 lane-muxing macros for J722S

[Roger Quadros]

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> The SERDES0 and SERDES1 instances of SERDES on J722S are single lane
> SERDES which are individually muxed across different peripherals.
> 
> LANE0 of SERDES0 is muxed between USB and CPSW while LANE0 of SERDES1 is
> muxed between PCIe and CPSW.
> 
> Define the lane-muxing macros to be used as the idle state values.
> 
> Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Reviewed-by: Roger Quadros <rogerq@kernel.org>

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[PATCH v5 6/7] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support

[Siddharth Vadapalli]

J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.

Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
file.

Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-7-s-vadapalli@ti.com/
Changes since v4:
- Based on Andrew's feedback at:
  https://lore.kernel.org/r/147d58a6-0cad-47b6-a069-755f835a77e9@ti.com/
  SERDES1 has also been disabled similar to SERDES0.

 arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 133 ++++++++++++++++++++++
 1 file changed, 133 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 84378fc839d6..b16f3a7cb109 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -5,7 +5,123 @@
  * Copyright (C) 2023-2024 Texas Instruments Incorporated - https://www.ti.com/
  */
 
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+	serdes_refclk: clk-0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <0>;
+	};
+};
+
 &cbass_main {
+	serdes_wiz0: phy@f000000 {
+		compatible = "ti,am64-wiz-10g";
+		ranges = <0x0f000000 0x0 0x0f000000 0x00010000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 279 0>, <&k3_clks 279 1>, <&serdes_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		num-lanes = <1>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+
+		assigned-clocks = <&k3_clks 279 1>;
+		assigned-clock-parents = <&k3_clks 279 5>;
+
+		serdes0: serdes@f000000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x0f000000 0x00010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz0 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 279 1>,
+						 <&k3_clks 279 1>,
+						 <&k3_clks 279 1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled"; /* Needs lane config */
+		};
+	};
+
+	serdes_wiz1: phy@f010000 {
+		compatible = "ti,am64-wiz-10g";
+		ranges = <0x0f010000 0x0 0x0f010000 0x00010000>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 280 0>, <&k3_clks 280 1>, <&serdes_refclk>;
+		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+		num-lanes = <1>;
+		#reset-cells = <1>;
+		#clock-cells = <1>;
+
+		assigned-clocks = <&k3_clks 280 1>;
+		assigned-clock-parents = <&k3_clks 280 5>;
+
+		serdes1: serdes@f010000 {
+			compatible = "ti,j721e-serdes-10g";
+			reg = <0x0f010000 0x00010000>;
+			reg-names = "torrent_phy";
+			resets = <&serdes_wiz1 0>;
+			reset-names = "torrent_reset";
+			clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+				 <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+			clock-names = "refclk", "phy_en_refclk";
+			assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+					  <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+					  <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+			assigned-clock-parents = <&k3_clks 280 1>,
+						 <&k3_clks 280 1>,
+						 <&k3_clks 280 1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#clock-cells = <1>;
+
+			status = "disabled"; /* Needs lane config */
+		};
+	};
+
+	pcie0_rc: pcie@f102000 {
+		compatible = "ti,j722s-pcie-host", "ti,j721e-pcie-host";
+		reg = <0x00 0x0f102000 0x00 0x1000>,
+		      <0x00 0x0f100000 0x00 0x400>,
+		      <0x00 0x0d000000 0x00 0x00800000>,
+		      <0x00 0x68000000 0x00 0x00001000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+		ranges = <0x01000000 0x00 0x68001000  0x00 0x68001000  0x00 0x0010000>,
+			 <0x02000000 0x00 0x68011000  0x00 0x68011000  0x00 0x7fef000>;
+		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
+		device_type = "pci";
+		max-link-speed = <3>;
+		num-lanes = <1>;
+		power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 259 0>, <&serdes1 CDNS_TORRENT_REFCLK_DRIVER>;
+		clock-names = "fck", "pcie_refclk";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0xff>;
+		vendor-id = <0x104c>;
+		device-id = <0xb010>;
+		cdns,no-bar-match-nbits = <64>;
+		ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x0>;
+		msi-map = <0x0 &gic_its 0x0 0x10000>;
+		status = "disabled";
+	};
+
 	usbss1: usb@f920000 {
 		compatible = "ti,j721e-usb";
 		reg = <0x00 0x0f920000 0x00 0x100>;
@@ -38,3 +154,20 @@ usb1: usb@31200000{
 		};
 	};
 };
+
+&main_conf {
+	serdes_ln_ctrl: mux-controller@4080 {
+		compatible = "reg-mux";
+		reg = <0x4080 0x14>;
+		#mux-control-cells = <1>;
+		mux-reg-masks = <0x00 0x3>, /* SERDES0 lane0 select */
+				<0x10 0x3>; /* SERDES1 lane0 select */
+	};
+};
+
+&wkup_conf {
+	pcie0_ctrl: pcie0-ctrl@4070 {
+		compatible = "ti,j784s4-pcie-ctrl", "syscon";
+		reg = <0x4070 0x4>;
+	};
+};
-- 
2.40.1


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Re: [PATCH v5 6/7] arm64: dts: ti: k3-j722s-main: Add SERDES and PCIe support

[Roger Quadros]

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> J722S SoC has two instances of SERDES namely SERDES0 and SERDES1 and one
> instance of PCIe namely PCIe0. Both SERDES0 and SERDES1 are single lane
> SERDES. The PCIe0 instance of PCIe is a Gen3 single lane PCIe controller.
> 
> Since SERDES and PCIe are not present on AM62P SoC, add the device-tree
> nodes corresponding to them in the J722S SoC specific "k3-j722s-main.dtsi"
> file.
> 
> Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Acked-by: Roger Quadros <rogerq@kernel.org>

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[PATCH v5 7/7] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM

[Siddharth Vadapalli]

Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
interface with the Type-C port via the USB hub, by configuring the pin P05
of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
mode of operation with Lane 0 of the SERDES0 instance of SERDES.

Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
v4:
https://lore.kernel.org/r/20240601121554.2860403-8-s-vadapalli@ti.com/
Changes since v4:
- Based on Andrew's feedback at:
  https://lore.kernel.org/r/183a9d15-939e-433b-84ba-8a64eb8ef3ec@ti.com/
  the `status = "okay";` line has been moved to the end of the
  `pcie0_rc` node referenced in k3-j722s-evm.dts following the updated
  ordering rules.
- The SERDES1 node has been enabled in the k3-j722s-evm.dts file since
  it has been disabled in the k3-j722s-main.dtsi file in the previous
  patch.

 arch/arm64/boot/dts/ti/k3-j722s-evm.dts | 73 +++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index bf3c246d13d1..253b02f0437d 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -9,7 +9,9 @@
 /dts-v1/;
 
 #include <dt-bindings/net/ti-dp83867.h>
+#include <dt-bindings/phy/phy.h>
 #include "k3-j722s.dtsi"
+#include "k3-serdes.h"
 
 / {
 	compatible = "ti,j722s-evm", "ti,j722s";
@@ -202,6 +204,12 @@ J722S_IOPAD(0x0130, PIN_OUTPUT, 0) /* (AG26) RGMII1_TXC */
 			J722S_IOPAD(0x012c, PIN_OUTPUT, 0) /* (AF25) RGMII1_TX_CTL */
 		>;
 	};
+
+	main_usb1_pins_default: main-usb1-default-pins {
+		pinctrl-single,pins = <
+			J722S_IOPAD(0x0258, PIN_INPUT, 0) /* (B27) USB1_DRVVBUS */
+		>;
+	};
 };
 
 &cpsw3g {
@@ -301,6 +309,13 @@ exp1: gpio@23 {
 				  "PCIe0_1L_RC_RSTz", "PCIe0_1L_PRSNT#",
 				  "ENET1_EXP_SPARE2", "ENET1_EXP_PWRDN",
 				  "PD_I2ENET1_I2CMUX_SELC_IRQ", "ENET1_EXP_RESETZ";
+
+		p05-hog {
+			/* P05 - USB2.0_MUX_SEL */
+			gpio-hog;
+			gpios = <5 GPIO_ACTIVE_HIGH>;
+			output-high;
+		};
 	};
 };
 
@@ -384,3 +399,61 @@ &sdhci1 {
 	status = "okay";
 	bootph-all;
 };
+
+&serdes_ln_ctrl {
+	idle-states = <J722S_SERDES0_LANE0_USB>,
+		      <J722S_SERDES1_LANE0_PCIE0_LANE0>;
+};
+
+&serdes0 {
+	status = "okay";
+	serdes0_usb_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_USB3>;
+		resets = <&serdes_wiz0 1>;
+	};
+};
+
+&serdes1 {
+	status = "okay";
+	serdes1_pcie_link: phy@0 {
+		reg = <0>;
+		cdns,num-lanes = <1>;
+		#phy-cells = <0>;
+		cdns,phy-type = <PHY_TYPE_PCIE>;
+		resets = <&serdes_wiz1 1>;
+	};
+};
+
+&pcie0_rc {
+	reset-gpios = <&exp1 18 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes1_pcie_link>;
+	phy-names = "pcie-phy";
+	status = "okay";
+};
+
+&usbss0 {
+	ti,vbus-divider;
+	status = "okay";
+};
+
+&usb0 {
+	dr_mode = "otg";
+	usb-role-switch;
+};
+
+&usbss1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&main_usb1_pins_default>;
+	ti,vbus-divider;
+	status = "okay";
+};
+
+&usb1 {
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	phys = <&serdes0_usb_link>;
+	phy-names = "cdns3,usb3-phy";
+};
-- 
2.40.1


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Re: [PATCH v5 7/7] arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM

[Roger Quadros]

On 04/06/2024 11:52, Siddharth Vadapalli wrote:
> Enable PCIe0 instance of PCIe in Root Complex mode of operation with Lane 0
> of the SERDES1 instance of SERDES. Also enable USB0 instance of USB to
> interface with the Type-C port via the USB hub, by configuring the pin P05
> of the GPIO expander on the EVM. Enable USB1 instance of USB in SuperSpeed
> mode of operation with Lane 0 of the SERDES0 instance of SERDES.
> 
> Co-developed-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>

Acked-by: Roger Quadros <rogerq@kernel.org>

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