From: "Kumar, Udit" <u-kumar1@ti.com>
To: Nishanth Menon <nm@ti.com>, Apurva Nandan <a-nandan@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Rafael J Wysocki <rafael@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Amit Kucheria <amitk@kernel.org>, Zhang Rui <rui.zhang@intel.com>,
<linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-pm@vger.kernel.org>, Keerthy J <j-keerthy@ti.com>,
<u-kumar1@ti.com>
Subject: Re: [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72
Date: Thu, 10 Aug 2023 17:23:39 +0530 [thread overview]
Message-ID: <ab69c4df-708f-8fff-a58b-a6531e15627b@ti.com> (raw)
In-Reply-To: <20230809190943.unpcbrinyn5ppei7@hydrated>
On 8/10/2023 12:39 AM, Nishanth Menon wrote:
> On 23:09-20230809, Apurva Nandan wrote:
>> From: Keerthy <j-keerthy@ti.com>
>>
>> Add 750M, 1G, 1.5G & 2G as the supported frequencies for A72.
>> This enables support for Dynamic Frequency Scaling(DFS)
>>
>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>> Signed-off-by: Apurva Nandan <a-nandan@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j7200.dtsi | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
>> index ef73e6d7e858..7222c453096f 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
>> @@ -48,6 +48,10 @@ cpu0: cpu@0 {
>> d-cache-line-size = <64>;
>> d-cache-sets = <256>;
>> next-level-cache = <&L2_0>;
>> + clocks = <&k3_clks 202 2>;
>> + clock-names = "cpu";
>> + operating-points-v2 = <&cpu0_opp_table>;
>> + #cooling-cells = <2>; /* min followed by max */
>> };
>>
>> cpu1: cpu@1 {
>> @@ -62,6 +66,30 @@ cpu1: cpu@1 {
>> d-cache-line-size = <64>;
>> d-cache-sets = <256>;
>> next-level-cache = <&L2_0>;
>> + clocks = <&k3_clks 203 0>;
>> + clock-names = "cpu";
>> + operating-points-v2 = <&cpu0_opp_table>;
>> + #cooling-cells = <2>; /* min followed by max */
>> + };
>> + };
>> +
>> + cpu0_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp4-2000000000 {
>> + opp-hz = /bits/ 64 <2000000000>;
>> + };
>> +
>> + opp3-1500000000 {
>> + opp-hz = /bits/ 64 <1500000000>;
>> + };
>> +
>> + opp2-1000000000 {
>> + opp-hz = /bits/ 64 <1000000000>;
>> + };
>> +
>> + opp1-750000000 {
>> + opp-hz = /bits/ 64 <750000000>;
>> };
>> };
>>
>> --
>> 2.34.1
>>
> Are you sure this is correct to enable all OPPs without efuse bit checks?
>
> https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
> 7.5 Operating Performance Points
> DRA821xC operates only upto 750MHz
> DRA821xE at 1GHz
> DRA821xL upto 1.5GHz and
> DRA821xT upto 2GHz
Looks, top SKUs is considered here .
After detecting which SKU we are running (I hope TRM should have this
information- through efuse or some other register)
I think, we can follow two approaches.
1) have OPP table for each SKU and select based SKUs type or
2) Do run time fixup by u-boot based upon SKU type
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next prev parent reply other threads:[~2023-08-10 11:54 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-09 17:39 [PATCH 0/3] Add support for thermal mitigation for K3 J7200 SoC Apurva Nandan
2023-08-09 17:39 ` [PATCH 1/3] thermal: k3_j72xx_bandgap: Add cooling device support Apurva Nandan
2023-08-16 10:15 ` Daniel Lezcano
2023-08-09 17:39 ` [PATCH 2/3] arm64: dts: ti: k3-j7200: Add the supported frequencies for A72 Apurva Nandan
2023-08-09 19:09 ` Nishanth Menon
2023-08-10 11:53 ` Kumar, Udit [this message]
2023-08-10 12:53 ` Nishanth Menon
2023-08-10 14:19 ` Kumar, Udit
2023-08-09 17:39 ` [PATCH 3/3] arm64: dts: ti: k3-j7200-thermal: Add cooling maps and cpu_alert trip at 75C Apurva Nandan
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