From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 03736EB1070 for ; Tue, 10 Mar 2026 15:35:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cgLJyArGG+jaAsH7dx4AJ8LQ1KU/3ffKN4NgpZZ7VIQ=; b=BLcHwH3Jt3CDLV5+WWSdfpyyfp ZylKylA4T4SOTGSoP2S3C8MlWoMRHpRYlDc8J3r7TYHst1TmvfYS7IjBvLb7lAYODWtuphuufgbE+ GNXEhpPKinNZHRAeXmAXEp8BhIGx8DQspJ3xAsqkVI+XsgDWkLuGYdzPjAcVj88tJDTIFzfAX/Qiv HnMCNVVPW1SkY7d+PgLH2NvvhrdOW6BJaJWcV+L+o3d47EDIsfAApPkF9rpu3xxnKmJyTgjDa79bE JTk6Cfrh9jyXQ9LiDeD5NjUVbQEI/G11sEyrvtFLpZt1vOtBwnXUuFCXGUlRkl+xpM/SNudSHCYyE ZKCLhXBw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vzz7K-00000009pAd-0pBj; Tue, 10 Mar 2026 15:35:30 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1vzz7I-00000009p9g-0Twa for linux-arm-kernel@lists.infradead.org; Tue, 10 Mar 2026 15:35:29 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 39A32169C; Tue, 10 Mar 2026 08:35:17 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B7A683F7BD; Tue, 10 Mar 2026 08:35:21 -0700 (PDT) Date: Tue, 10 Mar 2026 15:35:19 +0000 From: Catalin Marinas To: Vladimir Murzin Cc: Will Deacon , linux-arm-kernel@lists.infradead.org, Marc Zyngier , Oliver Upton , Lorenzo Pieralisi , Sudeep Holla , James Morse , Mark Rutland , Mark Brown , kvmarm@lists.linux.dev Subject: Re: [PATCH 3/4] arm64: errata: Work around early CME DVMSync acknowledgement Message-ID: References: <20260302165801.3014607-1-catalin.marinas@arm.com> <20260302165801.3014607-4-catalin.marinas@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260310_083528_269834_E94D32FB X-CRM114-Status: GOOD ( 27.52 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Thanks Vladimir, On Mon, Mar 09, 2026 at 10:13:20AM +0000, Vladimir Murzin wrote: > On 3/6/26 12:00, Catalin Marinas wrote: > >>> @@ -1358,6 +1360,85 @@ void do_sve_acc(unsigned long esr, struct pt_regs *regs) > >>> put_cpu_fpsimd_context(); > >>> } > >>> > >>> +#ifdef CONFIG_ARM64_ERRATUM_SME_DVMSYNC > >>> + > >>> +/* > >>> + * SME/CME erratum handling > >>> + */ > >>> +static cpumask_var_t sme_dvmsync_cpus; > >>> +static cpumask_var_t sme_active_cpus; > >>> + > >>> +void sme_set_active(unsigned int cpu) > >>> +{ > >>> + if (!cpus_have_final_cap(ARM64_WORKAROUND_SME_DVMSYNC)) > >>> + return; > >>> + if (!cpumask_test_cpu(cpu, sme_dvmsync_cpus)) > >>> + return; > >>> + > >>> + if (!test_bit(ilog2(MMCF_SME_DVMSYNC), ¤t->mm->context.flags)) > >>> + set_bit(ilog2(MMCF_SME_DVMSYNC), ¤t->mm->context.flags); > >>> + > >>> + cpumask_set_cpu(cpu, sme_active_cpus); > >>> + > >>> + /* > >>> + * Ensure subsequent (SME) memory accesses are observed after the > >>> + * cpumask and the MMCF_SME_DVMSYNC flag setting. > >>> + */ > >>> + smp_mb(); > >> > >> I can't convince myself that a DMB is enough here, as the whole issue > >> is that the SME memory accesses can be observed _after_ the TLB > >> invalidation. I'd have thought we'd need a DSB to ensure that the flag > >> updates are visible before the exception return. > > > > This is only to ensure that the sme_active_cpus mask is observed before > > any SME accesses. The mask is later used to decide whether to send the > > IPI. We have something like this: > > > > P0 > > STSET [sme_active_cpus] > > DMB > > SME access to [addr] > > > > P1 > > TLBI [addr] > > DSB > > LDR [sme_active_cpus] > > CBZ out > > Do IPI > > out: > > > > If P1 did not observe the STSET to [sme_active_cpus], P0 should have > > received and acknowledged the DVMSync before the STSET. Is your concern > > that P1 can observe the subsequent SME access but not the STSET? > > > > No idea whether herd can model this (I only put this in TLA+ for the > > main logic check but it doesn't do subtle memory ordering). > > JFYI, herd support for SME is still work-in-progress (specifically it misses > updates in cat), yet it can model VMSA. > > IIUC, expectation here is that either > - P1 observes sme_active_cpus, so we have to do_IPI or > - P0 observes TLBI (say shutdown, so it must fault) > > anything else is unexpected/forbidden. > > AArch64 A > variant=vmsa > { > int x=0; > int active=0; > > 0:X1=active; > 0:X3=x; > > 1:X0=(valid:0); > 1:X1=PTE(x); > 1:X2=x; > 1:X3=active; > > } > P0 | P1 ; > MOV W0,#1 | STR X0,[X1] ; > STR W0,[X1] (* sme_active_cpus *) | DSB ISH ; > DMB SY | LSR X9,X2,#12 ; > LDR W2,[X3] (* access to [addr] *) | TLBI VAAE1IS,X9 (* [addr] *) ; > | DSB ISH ; > | LDR W4,[X3] (* sme_active_cpus *) ; > > exists ~(1:X4=1 \/ fault(P0,x)) > > Is that correct understanding? Have I missed anything? Yes, I think that's correct. Another tweak specific to this erratum would be for P1 to do a store to x via another mapping after the TLBI+DSB and the P0 load should not see it. Even with the CPU erratum, if the P1 DVMSync is received/acknowledged by P0 before its STR to sme_active_cpus, I don't see how the subsequent SME load would overtake the STR given the DMB. The erratum messed up the DVMSync acknowledgement, not the barriers. -- Catalin