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[34.83.136.168]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-359f110991esm3573204a91.13.2026.03.10.13.00.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 13:00:49 -0700 (PDT) Date: Tue, 10 Mar 2026 20:00:45 +0000 From: Samiullah Khawaja To: Jason Gunthorpe Cc: Baolu Lu , Nicolin Chen , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, bhelgaas@google.com, rafael@kernel.org, lenb@kernel.org, praan@google.com, kees@kernel.org, smostafa@google.com, Alexander.Grest@microsoft.com, kevin.tian@intel.com, miko.lenczewski@arm.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, vsethi@nvidia.com Subject: Re: [PATCH v1 2/2] iommu/arm-smmu-v3: Recover ATC invalidate timeouts Message-ID: References: <20260305153911.GT972761@nvidia.com> <6416b7fe-0190-4c7b-9a62-5da7d5eea794@linux.intel.com> <20260306130006.GF1651202@nvidia.com> <20260306194312.GL1651202@nvidia.com> <20260306200321.GN1651202@nvidia.com> <20260306202652.GP1651202@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20260306202652.GP1651202@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260310_130052_570910_F7AFE53E X-CRM114-Status: GOOD ( 18.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Mar 06, 2026 at 04:26:52PM -0400, Jason Gunthorpe wrote: >On Fri, Mar 06, 2026 at 08:22:08PM +0000, Samiullah Khawaja wrote: > >> But do you think doing the timeout logic without fencing would be good >> enough? > >It is what ARM and AMD do, so I wouldn't object to it. I think without any back pressure to the caller, a device will be able to fill the invalidation queue with device IOTLB invalidations that get stuck until the HW timeout occurs. > >> Currently VT-d blocks itself, until it gets an Invalidation Timeout >> from HW, and system ends up in a hardlockup since interrupts are >> disabled. >> >> Are you concerned that if fencing is done without an RAS flow, the >> device might not be able to detect the failure (if it really needs ATS >> to work)? > >Yes, and then the device is badly locked because nothing will fix the >IOMMU fence. > >VFIO might fix it if it is restarted, but other approahces like >rmmod/insmod won't restore the broken device. > >So I'd rather see a more complete solution before we add fencing to >the iommu drivers. Minimally userspace doing a rmmod, flr, insmod >should be able to restore the device. > >Then auto-FLR through RAS could sit on top of that. > >> I am thinking, we can do translated fence and timeout change for VT-d. >> And the device can use existing RAS mechanism to recover itself. This >> way we atleast make sure that caller of flush can reuse the memory/IOVAs >> without UAFs. > >Without a larger framework to unfence I think this will get devices >stuck.. > >Jason