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[34.124.129.10]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-359f05edd69sm3807665a91.1.2026.03.10.12.40.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2026 12:41:02 -0700 (PDT) Date: Tue, 10 Mar 2026 19:40:56 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Nicolin Chen , will@kernel.org, robin.murphy@arm.com, joro@8bytes.org, bhelgaas@google.com, rafael@kernel.org, lenb@kernel.org, kees@kernel.org, baolu.lu@linux.intel.com, smostafa@google.com, Alexander.Grest@microsoft.com, kevin.tian@intel.com, miko.lenczewski@arm.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-pci@vger.kernel.org, vsethi@nvidia.com Subject: Re: [PATCH v1 2/2] iommu/arm-smmu-v3: Recover ATC invalidate timeouts Message-ID: References: <20260305153911.GT972761@nvidia.com> <20260305234158.GB1651202@nvidia.com> <20260306013347.GD1651202@nvidia.com> <20260306130202.GG1651202@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260306130202.GG1651202@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260310_124104_789940_2CA722A8 X-CRM114-Status: GOOD ( 25.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Mar 06, 2026 at 09:02:02AM -0400, Jason Gunthorpe wrote: > On Thu, Mar 05, 2026 at 09:06:17PM -0800, Nicolin Chen wrote: > > On Thu, Mar 05, 2026 at 09:33:47PM -0400, Jason Gunthorpe wrote: > > > On Thu, Mar 05, 2026 at 05:29:22PM -0800, Nicolin Chen wrote: > > > > > > > But arm_smmu_cmdq_issue_cmdlist() doesn't know when to push another > > > > CMD. In my case where ATC_INV irq occurs, the return value from the > > > > arm_smmu_cmdq_poll_until_sync() in the Step 5 is 0, and prods/cons > > > > are also matched. Actually, at this point that NOP ISR has already > > > > finished. > > > > > > Yes, you'd need a sneaky way to convay the error from the ISR to the > > > cmdlist code that didn't harm performance. Maybe we could come up with > > > something, but if it works replacing the NOP with flush sounds fairly > > > appealing - though can you do a single WORD edit to the STE that will > > > block translated requests? Zero EATS? > > > > Yea. I can give that a try. > > This also really needs to go after the invalidation changes because it > is feasible to also edit the lockless RCU invalidation list from the > ISR and disable the ATC for the failed device too. > > > > Also, will the SMMU start spamming with blocked translation events or > > > something that will need suppression too? > > > > CD.R=0 can suppress fault records, but we would need to override > > that in every CD of the device. > > That's too much to do from ISR, but maybe we can do it from a WQ.. > (Skimming through these, apologies if I'm losing context), shouldn't we do all that (marking it as an inv STE / abort STE, suppressing the faults) in the worker instead of trying to reset/recover the device? > Jason Thanks Praan