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Thu, 22 Jan 2026 23:41:08 -0800 (PST) Received: from [192.168.0.13] ([172.92.174.155]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3536dc506dbsm1276411a91.14.2026.01.22.23.41.07 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jan 2026 23:41:07 -0800 (PST) Message-ID: Date: Thu, 22 Jan 2026 23:39:29 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/2] dt-bindings: ethernet: eswin: add clock sampling control To: Andrew Lunn , =?UTF-8?B?5p2O5b+X?= Cc: devicetree@vger.kernel.org, andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, rmk+kernel@armlinux.org.uk, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, ningyu@eswincomputing.com, linmin@eswincomputing.com, pinkesh.vaghela@einfochips.com, weishangjuan@eswincomputing.com References: <20260109080601.1262-1-lizhi2@eswincomputing.com> <20260109080859.1285-1-lizhi2@eswincomputing.com> <00b7b42f-2f9d-402a-82f0-21641ea894a1@lunn.ch> <308b676.2d03.19bb0caebed.Coremail.lizhi2@eswincomputing.com> <59cec617-0189-4dc3-bc3f-6346155a62ae@lunn.ch> <4e2a55e7.3662.19be8cb9c3c.Coremail.lizhi2@eswincomputing.com> Content-Language: en-US From: Bo Gan In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260122_234110_234229_56C9C7BC X-CRM114-Status: GOOD ( 14.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Andrew, On 1/22/26 19:19, Andrew Lunn wrote: >>> You say internal. So the skew is fixed, it is a property of the >>> silicon? If so, why a DT property? Why not just hard code it in the >>> driver? Since it is internal, different boards should not need it set >>> differently? >>> >> Thanks for the question. >> >> EIC7700 has two Ethernet MACs. Only eth1 has this internal RXC/RXD skew, >> eth0 does not. >> >> So this is not a chip-wide constant that can be hardcoded in the driver. >> We need a way to distinguish the two MAC instances, which is why this is >> described per-port in DTS. > > I assume the address of the interface is fixed. So you can just key > off that to distinguish the two instances. > > Since this is an internal property, not a board property, it is not > clear it actually belongs on DT. > > Andrew IMO, they should be in DT to provide maximum flexibility. The SoC .dtsi can provide some sane defaults, and the board vendor can later override them if the mac/phy requires further tuning. Applying such tuning by the address of MAC seems messy and it hides the parameters used behind driver. Through DT, everything becomes really clear. I assume this is not uncommon: E.g., starfive/jh7110: https://lore.kernel.org/all/20230714104521.18751-3-samin.guo@starfivetech.com/ BTW, no need to worry about backward compat. ESWIN hasn't checked-in any DT for eth yet. As you and Russell said, they need to do it, pronto. Bo