From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C47BF53D80 for ; Mon, 16 Mar 2026 17:38:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=d6hlPphJxWUigGrZ1LWvkU5ZGSyX49GbZz2uIW3xTMQ=; b=sSPPm5VpoVx3DIbL2PdokyvSfl 2jGxZdqc+7gmuBSh+t7gABT4MM7LNws1/I+dNLSysnGgSE/V+xsnbWCPTcaVEfkKNnvXN/DUv4Tjg TjLjw6gty4x/KJPaCMauDp74kxsFytLKaXikHa/WXrca1yai0tm/rSqk9OnW1Xt9/xH8N8e9Mwu83 GeCm9x3KXt/WyWFXQhiAomXomEcCqGxeBmT+ylPKqPXPCbyGA2X6FiE44d3YnC+vFl7di76e+rTta 9+OVCbUfGk8ZSN88DyHU85n5K5ElKVVcIz10/7+bdWqVjEaP9SZGu1N7RNAGYpdZUDWRTL6Qk3It9 CSqbjHxA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w2BtC-00000004amj-1JXc; Mon, 16 Mar 2026 17:38:02 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.98.2 #2 (Red Hat Linux)) id 1w2Bt9-00000004alt-3o4g for linux-arm-kernel@lists.infradead.org; Mon, 16 Mar 2026 17:38:01 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7857314BF; Mon, 16 Mar 2026 10:37:51 -0700 (PDT) Received: from arm.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 108903F73B; Mon, 16 Mar 2026 10:37:54 -0700 (PDT) Date: Mon, 16 Mar 2026 17:37:52 +0000 From: Catalin Marinas To: Mark Brown Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Will Deacon , Paolo Bonzini , Jonathan Corbet , Shuah Khan , Oliver Upton , Dave Martin , Fuad Tabba , Mark Rutland , Ben Horgan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, Peter Maydell , Eric Auger Subject: Re: [PATCH v10 02/30] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Message-ID: References: <20260306-kvm-arm64-sme-v10-0-43f7683a0fb7@kernel.org> <20260306-kvm-arm64-sme-v10-2-43f7683a0fb7@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260306-kvm-arm64-sme-v10-2-43f7683a0fb7@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260316_103800_004707_9AA62E0E X-CRM114-Status: GOOD ( 16.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Mar 06, 2026 at 05:00:54PM +0000, Mark Brown wrote: > Currently we enable EL0 and EL1 access to FA64 and ZT0 at boot and leave > them enabled throughout the runtime of the system. When we add KVM support > we will need to make this configuration dynamic, these features may be > disabled for some KVM guests. Since the host kernel saves the floating > point state for non-protected guests and we wish to avoid KVM having to > reload the floating point state needlessly on guest reentry let's move the > configuration of these enables to the floating point state reload. > > We provide a helper which does the configuration as part of a > read/modify/write operation along with the configuration of the task VL, > then update the floating point state load and SME access trap to use it. > We also remove the setting of the enable bits from the CPU feature > identification and resume paths. There will be a small overhead from > setting the enables one at a time but this should be negligible in the > context of the state load or access trap. In order to avoid compiler > warnings due to unused variables in !CONFIG_ARM64_SME cases we avoid > storing the vector length in temporary variables. > > Signed-off-by: Mark Brown Reviewed-by: Catalin Marinas