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* [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support
@ 2026-03-16 16:19 Suzuki K Poulose
  2026-03-16 17:54 ` Catalin Marinas
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Suzuki K Poulose @ 2026-03-16 16:19 UTC (permalink / raw)
  To: linux-arm-kernel
  Cc: mark.rutland, maz, linux-kernel, aneesh.kumar, steven.price,
	Suzuki K Poulose, Catalin Marinas, Will Deacon

With LPA/LPA2, the top bits of the PFN (Bits[51:48]) end up in the lower bits
of the PTE. So, simply creating a mask of the "top IPA bit" doesn't work well
for these configurations to set the "top" bit at the output of Stage1
translation.

Fix this by using the __phys_to_pte_val() to do the right thing for all
configurations.

Tested using, kvmtool, placing the memory at a higher address (-m <size>@<Addr>).

 e.g:
 # lkvm run --realm -c 4 -m 512M@@128T -k Image --console serial

 sh-5.0# dmesg | grep "LPA2\|RSI"
[    0.000000] RME: Using RSI version 1.0
[    0.000000] CPU features: detected: 52-bit Virtual Addressing (LPA2)
[    0.777354] CPU features: detected: 52-bit Virtual Addressing for KVM (LPA2)

Fixes: 399306954996 ("arm64: realm: Query IPA size from the RMM")
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Steven Price <steven.price@arm.com>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 arch/arm64/kernel/rsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kernel/rsi.c b/arch/arm64/kernel/rsi.c
index c64a06f58c0b..9e846ce4ef9c 100644
--- a/arch/arm64/kernel/rsi.c
+++ b/arch/arm64/kernel/rsi.c
@@ -12,6 +12,7 @@
 
 #include <asm/io.h>
 #include <asm/mem_encrypt.h>
+#include <asm/pgtable.h>
 #include <asm/rsi.h>
 
 static struct realm_config config;
@@ -146,7 +147,7 @@ void __init arm64_rsi_init(void)
 		return;
 	if (WARN_ON(rsi_get_realm_config(&config)))
 		return;
-	prot_ns_shared = BIT(config.ipa_bits - 1);
+	prot_ns_shared = __phys_to_pte_val(BIT(config.ipa_bits - 1));
 
 	if (arm64_ioremap_prot_hook_register(realm_ioremap_hook))
 		return;
-- 
2.43.0



^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support
  2026-03-16 16:19 [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support Suzuki K Poulose
@ 2026-03-16 17:54 ` Catalin Marinas
  2026-03-18 11:36 ` Steven Price
  2026-03-19 13:48 ` Will Deacon
  2 siblings, 0 replies; 4+ messages in thread
From: Catalin Marinas @ 2026-03-16 17:54 UTC (permalink / raw)
  To: Suzuki K Poulose
  Cc: linux-arm-kernel, mark.rutland, maz, linux-kernel, aneesh.kumar,
	steven.price, Will Deacon

On Mon, Mar 16, 2026 at 04:19:01PM +0000, Suzuki K Poulose wrote:
> With LPA/LPA2, the top bits of the PFN (Bits[51:48]) end up in the lower bits
> of the PTE. So, simply creating a mask of the "top IPA bit" doesn't work well
> for these configurations to set the "top" bit at the output of Stage1
> translation.
> 
> Fix this by using the __phys_to_pte_val() to do the right thing for all
> configurations.
> 
> Tested using, kvmtool, placing the memory at a higher address (-m <size>@<Addr>).
> 
>  e.g:
>  # lkvm run --realm -c 4 -m 512M@@128T -k Image --console serial
> 
>  sh-5.0# dmesg | grep "LPA2\|RSI"
> [    0.000000] RME: Using RSI version 1.0
> [    0.000000] CPU features: detected: 52-bit Virtual Addressing (LPA2)
> [    0.777354] CPU features: detected: 52-bit Virtual Addressing for KVM (LPA2)
> 
> Fixes: 399306954996 ("arm64: realm: Query IPA size from the RMM")
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Steven Price <steven.price@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support
  2026-03-16 16:19 [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support Suzuki K Poulose
  2026-03-16 17:54 ` Catalin Marinas
@ 2026-03-18 11:36 ` Steven Price
  2026-03-19 13:48 ` Will Deacon
  2 siblings, 0 replies; 4+ messages in thread
From: Steven Price @ 2026-03-18 11:36 UTC (permalink / raw)
  To: Suzuki K Poulose, linux-arm-kernel
  Cc: mark.rutland, maz, linux-kernel, aneesh.kumar, Catalin Marinas,
	Will Deacon

On 16/03/2026 16:19, Suzuki K Poulose wrote:
> With LPA/LPA2, the top bits of the PFN (Bits[51:48]) end up in the lower bits
> of the PTE. So, simply creating a mask of the "top IPA bit" doesn't work well
> for these configurations to set the "top" bit at the output of Stage1
> translation.
> 
> Fix this by using the __phys_to_pte_val() to do the right thing for all
> configurations.
> 
> Tested using, kvmtool, placing the memory at a higher address (-m <size>@<Addr>).
> 
>  e.g:
>  # lkvm run --realm -c 4 -m 512M@@128T -k Image --console serial
> 
>  sh-5.0# dmesg | grep "LPA2\|RSI"
> [    0.000000] RME: Using RSI version 1.0
> [    0.000000] CPU features: detected: 52-bit Virtual Addressing (LPA2)
> [    0.777354] CPU features: detected: 52-bit Virtual Addressing for KVM (LPA2)
> 
> Fixes: 399306954996 ("arm64: realm: Query IPA size from the RMM")
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Steven Price <steven.price@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Reviewed-by: Steven Price <steven.price@arm.com>

> ---
>  arch/arm64/kernel/rsi.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/kernel/rsi.c b/arch/arm64/kernel/rsi.c
> index c64a06f58c0b..9e846ce4ef9c 100644
> --- a/arch/arm64/kernel/rsi.c
> +++ b/arch/arm64/kernel/rsi.c
> @@ -12,6 +12,7 @@
>  
>  #include <asm/io.h>
>  #include <asm/mem_encrypt.h>
> +#include <asm/pgtable.h>
>  #include <asm/rsi.h>
>  
>  static struct realm_config config;
> @@ -146,7 +147,7 @@ void __init arm64_rsi_init(void)
>  		return;
>  	if (WARN_ON(rsi_get_realm_config(&config)))
>  		return;
> -	prot_ns_shared = BIT(config.ipa_bits - 1);
> +	prot_ns_shared = __phys_to_pte_val(BIT(config.ipa_bits - 1));
>  
>  	if (arm64_ioremap_prot_hook_register(realm_ioremap_hook))
>  		return;



^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support
  2026-03-16 16:19 [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support Suzuki K Poulose
  2026-03-16 17:54 ` Catalin Marinas
  2026-03-18 11:36 ` Steven Price
@ 2026-03-19 13:48 ` Will Deacon
  2 siblings, 0 replies; 4+ messages in thread
From: Will Deacon @ 2026-03-19 13:48 UTC (permalink / raw)
  To: linux-arm-kernel, Suzuki K Poulose
  Cc: catalin.marinas, kernel-team, Will Deacon, mark.rutland, maz,
	linux-kernel, aneesh.kumar, steven.price

On Mon, 16 Mar 2026 16:19:01 +0000, Suzuki K Poulose wrote:
> With LPA/LPA2, the top bits of the PFN (Bits[51:48]) end up in the lower bits
> of the PTE. So, simply creating a mask of the "top IPA bit" doesn't work well
> for these configurations to set the "top" bit at the output of Stage1
> translation.
> 
> Fix this by using the __phys_to_pte_val() to do the right thing for all
> configurations.
> 
> [...]

Applied to arm64 (for-next/fixes), thanks!

[1/1] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support
      https://git.kernel.org/arm64/c/8c6e9b60f5c7

Cheers,
-- 
Will

https://fixes.arm64.dev
https://next.arm64.dev
https://will.arm64.dev


^ permalink raw reply	[flat|nested] 4+ messages in thread

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2026-03-16 16:19 [PATCH] arm64: realm: Fix PTE_NS_SHARED for 52bit PA support Suzuki K Poulose
2026-03-16 17:54 ` Catalin Marinas
2026-03-18 11:36 ` Steven Price
2026-03-19 13:48 ` Will Deacon

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