Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Mark Rutland <mark.rutland@arm.com>]

On Tue, Mar 17, 2026 at 08:16:44AM +0530, Anshuman Khandual wrote:
> On 13/03/26 3:29 PM, Mark Rutland wrote:
> > On Fri, Mar 13, 2026 at 05:38:57AM +0000, Anshuman Khandual wrote:
> >> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
> >> ensures that MMU stage-2 translation remain disabled.
> > 
> > As Marc noted, that's not true -- whether stage 2 is enabled is governed
> > entirely by HCR_EL2.VM.
> > > The only reason to initialize VTCR_EL2 here would be if some field in
> > VTCR_EL2 applies when stage 2 is *disabled*.
> 
> Understood. Something similar to VTTBR_EL2.VMID field which
> gets into tagged TLB entries for EL0/EL1 translation regime
> even when stage-2 is not enabled via HCR_EL2_VM.
> 
> But wondering if VTTBR_EL2.VMID gets cleaned up should not
> it also be followed by a "tlbi vmalls12e1 --> dsb --> isb"
> sequence to clear existing stale TLB entries ?

We only need to do that before they're used.

> >> Although clearing out VTTBR_EL2 probably should have been sufficient
> >> but adding VTCR_EL2 improves overall safety.
> > 
> > It's unhelpful to send patches like this with unclear or non-existent
> > rationale, and vague statements about what the patch might do. Was there
> 
> The commit message could have been more detailed and explicit
> about its rationale. Although the intent here was to ensure
> improved safety during S2 MMU context initialization.

Sorry, but "improvied safety" is meaningless unless you can express a
specific concern.

You don't appear to have done reading to understand basic concepts in
this area (e.g. *when* Stage 2 is enabled, and which system register
fields affect this), and you're wasting reviewers' time with incorrect
theories about how the architecture works, where *you* could do the
necessary work.

Please do that background reading *before* sending patches like this,
and please do not send patches without a more concrete rationale.

> > some specific reason to send this? e.g.
> > 
> > * Did you have any specific reason to believe that setting some field in
> >   VTCR_EL2 was necessary? e.g. is there some misleading documentation,
> >   or comment elsewhere in the kernel?
> > 
> > * Are you trying to fix some problem you've encountered, but haven't
> >   managed to debug?
> > 
> > * Was this purely from inspection?
> 
> This was from code inspection while navigating S2 MMU context
> initialization and management.

Ok. As above, please do background reading before sending patches like
this.

Mark.

> > Mark.
> > 
> >> Cc: Catalin Marinas <catalin.marinas@arm.com>
> >> Cc: Will Deacon <will@kernel.org>
> >> Cc: Marc Zyngier <maz@kernel.org>
> >> Cc: Oliver Upton <oupton@kernel.org>
> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> Cc: linux-arm-kernel@lists.infradead.org
> >> Cc: linux-kernel@vger.kernel.org
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >> ---
> >>  arch/arm64/include/asm/el2_setup.h | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> >> index 85f4c1615472..2c88033591bb 100644
> >> --- a/arch/arm64/include/asm/el2_setup.h
> >> +++ b/arch/arm64/include/asm/el2_setup.h
> >> @@ -189,6 +189,7 @@
> >>  /* Stage-2 translation */
> >>  .macro __init_el2_stage2
> >>  	msr	vttbr_el2, xzr
> >> +	msr	vtcr_el2, xzr
> >>  .endm
> >>  
> >>  /* GICv3 system register access */
> >> -- 
> >> 2.30.2
> >>
>