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Wed, 18 Mar 2026 20:13:45 -0700 Received: from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 18 Mar 2026 20:13:44 -0700 Received: from Asurada-Nvidia (10.127.8.9) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 18 Mar 2026 20:13:43 -0700 Date: Wed, 18 Mar 2026 20:13:42 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: "will@kernel.org" , "robin.murphy@arm.com" , "joro@8bytes.org" , "bhelgaas@google.com" , "jgg@nvidia.com" , "rafael@kernel.org" , "lenb@kernel.org" , "praan@google.com" , "baolu.lu@linux.intel.com" , "xueshuai@linux.alibaba.com" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , Vikram Sethi Subject: Re: [PATCH v2 3/7] iommu: Add iommu_report_device_broken() to quarantine a broken device Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: WAWIwwAXa813hzEjcuOZp8OfUPa9WRQDJdqsYd8Fp+ZxCLz1jvuw+bDo1MwR75OfCJqP3jOiDVDUqi2f8c8JwXYQd6wNUFdP3d5DLniOjIz2ijDnZQmvPoCSO/MHfJyz3UubM974gVLLnb9eM3kpaaW4OfDS2LlqfDe3yUdJ4vfUi8dKl3eCT71OQhnzXrIrjKFsRXrryJqya83X1/+5XLMt3aHbDgERabtHWaAxx1bOxLEsuoz4xZTDIyT5vAEgJlDSpFjIOAPAZJMkSjDhT2mCkILVkLMtuVv3C5NNAxpwPpUYm28ozo7sDjWSbUbPfxmsvIo3YfeGTqThYrbf8BrzZJz1iOaD8GTnVpu8MrSvor2N4D5QW86ec4Tl33ODKMZtHuKM0mkHRTxczHelOkar7zPyvOmX0ySK6fKIdgiEKeueHiKuUbyj0PMxNDYU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 03:14:02.4780 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 210b9492-a01f-4a44-3228-08de85659252 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000A6734.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4358 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260319_031409_976876_A0F30FC0 X-CRM114-Status: GOOD ( 27.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 19, 2026 at 02:35:33AM +0000, Tian, Kevin wrote: > > > > + scoped_guard(mutex, &group->mutex) { > > > > + /* Do not block the device again if it has been recovered */ > > > > + if (!READ_ONCE(group->requires_reset)) > > > > + goto out_put; > > > > + if (list_is_singular(&group->devices)) { > > > > + /* Note: only support group with a single device */ > > > > > > this series is about fixing a vulnerability. Then it sounds incomplete to > > > leave certain configuration still under risk. Probably we should first > > > ensure ATS can be enabled only in singleton group, just like how we > > > did for pci_enable_pasid()? > > > > I understand your concern. But I am not very sure about applying > > limitation to ATS support. Would this block some existing cases? > > what about just throwing out a message to warn that enabling ATS > in a non-singleton iommu group may suffer from unquarantined > situation if any device in the group triggers a ATC invalidation timeout? Yes. Baolu suggested the same, we could move this condition into iommu_report_device_broken(). > > > > + /* > > > > + * Quarantine the device completely. This will be cleared > > > > upon > > > > + * a pci_dev_reset_iommu_done() call indicating the recovery. > > > > + */ > > > > + pci_dev_lock(pdev); > > > > + pci_dev_reset_iommu_prepare(pdev); > > > > > > let's rename it to iommu_quarantine_device() to be called here. then > > > have another wrapper pci_dev_reset_iommu_prepare() to call it too. > > > > > > this path has nothing to do with reset. > > > > But the implementation of that iommu_quarantine_device would be > > still to shift to resetting_domain. Perhaps, we can rename that > > to quarantine_domain or so. > > yes let's rename that too. the purpose of this function is clearly about > quarantine. reset is just one user of it. OK. I will make it happen. Nicolin