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Wed, 18 Mar 2026 20:12:06 -0700 Received: from Asurada-Nvidia (10.127.8.9) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20 via Frontend Transport; Wed, 18 Mar 2026 20:12:05 -0700 Date: Wed, 18 Mar 2026 20:12:04 -0700 From: Nicolin Chen To: "Tian, Kevin" CC: Samiullah Khawaja , "will@kernel.org" , "robin.murphy@arm.com" , "joro@8bytes.org" , "bhelgaas@google.com" , "jgg@nvidia.com" , "rafael@kernel.org" , "lenb@kernel.org" , "praan@google.com" , "baolu.lu@linux.intel.com" , "xueshuai@linux.alibaba.com" , "linux-arm-kernel@lists.infradead.org" , "iommu@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , Vikram Sethi Subject: Re: [PATCH v2 4/7] iommu/arm-smmu-v3: Mark ATC invalidate timeouts via lockless bitmap Message-ID: References: <0c5525367cc67ccc84a675544d1d9f8462704065.1773774441.git.nicolinc@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: L7h2pk0xxAj7g/xdyBKU9DPDQ/SlW47Q82ptw1cNClMJMMqiP1P8mI1hbZ70GDvXdL4e4oSdpaJggCBgzBmke/QrB9B68QYRudTyjvOS1ODxQGzuKSTXxpo4GGv58X7X/tEYBAQ94CtWrRhocND+LAwlPmCoOU6QhOAGEad6WyzfKGaabAbYUDPSPuOaPQScfV3AG9ZpuNULpAAnkgniLsiz9n9/58XnE6HKp2KMrbJ95WRXVsTwzUmQxzkdeME4c/CbKq1WMJuoNx0fw5pM4GnInpp7TpKDheYsw3VTJxSSh68BVkFfw8IEhR1/kNycz5Wgu5ZKJDjcNYq0jgWZRQ5l/PON0thHHmQLhIRa7sLDcqqQWx6RjEoph1NJxcz0V+bUrvrCL4pZPC/0YHX54kwZJJIAhCxF76FnUKs4E0kXGs0ZINFEHjHgOKojvIyL X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Mar 2026 03:12:15.3722 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6dbc8a8-e36e-4f77-164d-08de85655275 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636C.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6221 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260318_201223_864736_71EC0E9D X-CRM114-Status: GOOD ( 22.86 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Mar 19, 2026 at 03:08:05AM +0000, Tian, Kevin wrote: > > From: Samiullah Khawaja > > Sent: Thursday, March 19, 2026 6:07 AM > > > > Hi Nicolin, > > > > On Wed, Mar 18, 2026 at 12:26:33PM -0700, Nicolin Chen wrote: > > >On Wed, Mar 18, 2026 at 07:36:20AM +0000, Tian, Kevin wrote: > > >> > From: Nicolin Chen > > >> > Sent: Wednesday, March 18, 2026 3:16 AM > > >> > > > >> > An ATC invalidation timeout is a fatal error. While the SMMUv3 > > hardware is > > >> > aware of the timeout via a GERROR interrupt, the driver thread issuing > > the > > >> > commands lacks a direct mechanism to verify whether its specific batch > > was > > >> > the cause or not, as polling the CMD_SYNC status doesn't natively return > > a > > >> > failure code, making it very difficult to coordinate per-device recovery. > > >> > > > >> > Introduce an atc_sync_timeouts bitmap in the cmdq structure to bridge > > this > > >> > gap. When the ISR detects an ATC timeout, set the bit corresponding to > > the > > >> > physical CMDQ index of the faulting CMD_SYNC command. > > >> > > > >> > > >> It's nice to see the ability of allowing sw to identify the faulting sync > > command > > >> upon an ATC timeout! On VT-d it's not feasible when multiple wait > > descriptors > > >> (similar to CMD_SYNC) are in-fly... :/ > > > > > >Actually SMMU doesn't know which device is faulting when CMD_SYNC > > > > VT-d is able to find out the SID of the device for which the device TLB > > invalidation timed-out occured by using the SID reported in the > > "Invalidation Queue Error Record Register" (VT-d Specs 11.4.9.9). > > yes. but when there are multiple submissions (each with a wait descriptor) > fetched/handled by the hw and then an invalidation timeout comes, all > pending wait descriptors will be aborted (not just the one corresponding > to the timeout). In this case all affected submitters need to re-try. This sounds similar to SMMU then. Nicolin