Re: [PATCH v3 1/2] dmaengine: xilinx_dma: Fix CPU stall in xilinx_dma_poll_timeout

[Frank Li <Frank.li@nxp.com>]

On Wed, Apr 01, 2026 at 12:56:32PM +0200, Alex Bereza wrote:
> Currently when calling xilinx_dma_poll_timeout with delay_us=0 and a
> condition that is never fulfilled, the CPU busy-waits for prolonged time
> and the timeout triggers only with a massive delay causing a CPU stall.
>
> This happens due to a huge underestimation of wall clock time in
> poll_timeout_us_atomic. Commit 7349a69cf312 ("iopoll: Do not use
> timekeeping in read_poll_timeout_atomic()") changed the behavior to no
> longer use ktime_get at the expense of underestimation of wall clock
> time which appears to be very large for delay_us=0. Instead of timing
> out after approximately XILINX_DMA_LOOP_COUNT microseconds, the timeout
> takes XILINX_DMA_LOOP_COUNT * 1000 * (time that the overhead of the for
> loop in poll_timeout_us_atomic takes) which is in the range of several
> minutes for XILINX_DMA_LOOP_COUNT=1000000. Fix this by using a non-zero
> value for delay_us. Use delay_us=10 to keep the delay in the hot path of
> starting DMA transfers minimal but still avoid CPU stalls in case of
> unexpected hardware failures.
>
> One-off measurement with delay_us=0 causes the cpu to busy wait around 7
> minutes in the timeout case. After applying this patch with delay_us=10
> the measured timeout was 1053428 microseconds which is roughly
> equivalent to the expected 1000000 microseconds specified in
> XILINX_DMA_LOOP_COUNT.
>
> Add a constant XILINX_DMA_POLL_DELAY_US for delay_us value.
>
> Fixes: 9495f2648287 ("dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop's")
> Fixes: 7349a69cf312 ("iopoll: Do not use timekeeping in read_poll_timeout_atomic()")
> Signed-off-by: Alex Bereza <alex@bereza.email>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  drivers/dma/xilinx/xilinx_dma.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 02a05f215614..345a738bab2c 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -167,6 +167,8 @@
>
>  /* Delay loop counter to prevent hardware failure */
>  #define XILINX_DMA_LOOP_COUNT		1000000
> +/* Delay between polls (avoid a delay of 0 to prevent CPU stalls) */
> +#define XILINX_DMA_POLL_DELAY_US	10
>
>  /* AXI DMA Specific Registers/Offsets */
>  #define XILINX_DMA_REG_SRCDSTADDR	0x18
> @@ -1332,7 +1334,8 @@ static int xilinx_dma_stop_transfer(struct xilinx_dma_chan *chan)
>
>  	/* Wait for the hardware to halt */
>  	return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
> -				       val & XILINX_DMA_DMASR_HALTED, 0,
> +				       val & XILINX_DMA_DMASR_HALTED,
> +				       XILINX_DMA_POLL_DELAY_US,
>  				       XILINX_DMA_LOOP_COUNT);
>  }
>
> @@ -1347,7 +1350,8 @@ static int xilinx_cdma_stop_transfer(struct xilinx_dma_chan *chan)
>  	u32 val;
>
>  	return xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
> -				       val & XILINX_DMA_DMASR_IDLE, 0,
> +				       val & XILINX_DMA_DMASR_IDLE,
> +				       XILINX_DMA_POLL_DELAY_US,
>  				       XILINX_DMA_LOOP_COUNT);
>  }
>
> @@ -1364,7 +1368,8 @@ static void xilinx_dma_start(struct xilinx_dma_chan *chan)
>
>  	/* Wait for the hardware to start */
>  	err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMASR, val,
> -				      !(val & XILINX_DMA_DMASR_HALTED), 0,
> +				      !(val & XILINX_DMA_DMASR_HALTED),
> +				      XILINX_DMA_POLL_DELAY_US,
>  				      XILINX_DMA_LOOP_COUNT);
>
>  	if (err) {
> @@ -1780,7 +1785,8 @@ static int xilinx_dma_reset(struct xilinx_dma_chan *chan)
>
>  	/* Wait for the hardware to finish reset */
>  	err = xilinx_dma_poll_timeout(chan, XILINX_DMA_REG_DMACR, tmp,
> -				      !(tmp & XILINX_DMA_DMACR_RESET), 0,
> +				      !(tmp & XILINX_DMA_DMACR_RESET),
> +				      XILINX_DMA_POLL_DELAY_US,
>  				      XILINX_DMA_LOOP_COUNT);
>
>  	if (err) {
>
> --
> 2.53.0
>