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[83.233.6.197]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-38c6a848cddsm520711fa.13.2026.03.26.05.17.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Mar 2026 05:17:52 -0700 (PDT) Date: Thu, 26 Mar 2026 13:17:50 +0100 From: Marcus Folkesson To: Wolfram Sang , Peter Rosin , Michael Hennerich , Bartosz Golaszewski , Andi Shyti , Andy Shevchenko , Bartosz Golaszewski Cc: linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v9 0/5] I2C Mux per channel bus speed Message-ID: References: <20260324-i2c-mux-v9-0-5292b0608243@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260324-i2c-mux-v9-0-5292b0608243@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260326_051755_473930_7CD97CF5 X-CRM114-Status: GOOD ( 24.31 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Mar 24, 2026 at 02:54:14PM +0100, Marcus Folkesson wrote: > This was a RFC on how to implement a feature to have different bus > speeds on different channels with an I2C multiplexer/switch. > As no major complaints on the design came up during the review, I > decided to submit the series without the RFC tag. > > The benefit with this feature is that you may group devices after > the fastest bus speed they can handle. > A real-world example is that you could have e.g. a display running @400kHz > and a smart battery running @100kHz using the same I2C controller. > > There are many corner cases where this may cause a problem for some > hardware topologies. I've tried to describe those I could think of > in the documentation, see Patch #5. > > E.g. one risk is that if the mux driver does not disconnect channels > when Idle, this may cause a higher frequency to "leak" through to > devices that are supposed to run at lower bus speed. > This is not only a "problem" for changing bus speed but could also be > an issue for potential address conflicts. > > This patchset has been used and tested heavily the last months > on a custom board based on a da850 (DaVinci) platform. > > The implementation is split up into several patches: > > Patch #1 Introduce a callback for the i2c controller to set bus speed > Patch #2 Introduce functionality to adjust bus speed depending on mux > channel. > Patch #3 Cleanup i2c-davinci driver a bit to prepare it for set_clk_freq > Parch #4 Implement set_clk_freq for the i2c-davinci driver > Parch #5 Update documentation with this feature > > Signed-off-by: Marcus Folkesson > --- Peter, Do you have any feedback on this new approach? Thanks in advance, Marcus