[BOOTWRAPPER][PATCH] Make GICv3.1 extended ranges available to non-secure

Marc Zyngier
2019-07-23T11:56:06Z

If we have a GICv3.1-capable system, configure the EPPI/ESPI ranges
to be accessible from the non-secure world.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
gic-v3.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/gic-v3.c b/gic-v3.c
index 476f703..4b733ba 100644
--- a/gic-v3.c
+++ b/gic-v3.c
@@ -17,6 +17,8 @@
#define GICD_TYPER 0x4
#define GICD_IGROUP0 0x80
#define GICD_IGRPMOD0 0xd00
+#define GICD_IGROUPR0E 0x1000
+#define GICD_IGRPMODR0E 0x3400

#define GICD_CTLR_EnableGrp0 (1 << 0)
#define GICD_CTLR_EnableGrp1ns (1 << 1)
@@ -57,6 +59,7 @@ void gic_secure_init_primary(void)
* ChildrenAsleep to be 0.
*/
uint32_t waker = raw_readl(gicr_ptr + GICR_WAKER);
+ uint32_t regs;
waker &= ~GICR_WAKER_ProcessorSleep;
raw_writel(waker, gicr_ptr + GICR_WAKER);
dsb(st);
@@ -72,8 +75,11 @@ void gic_secure_init_primary(void)
typer = raw_readl(gicr_ptr + GICR_TYPER);

gicr_ptr += 0x10000; /* Go to SGI_Base */
- raw_writel(~0x0, gicr_ptr + GICR_IGROUP0);
- raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0);
+ regs = 1 + ((typer >> 27) & 0x1f);
+ for (i = 0; i < regs; i++) {
+ raw_writel(~0x0, gicr_ptr + GICR_IGROUP0 + i * 4);
+ raw_writel(0x0, gicr_ptr + GICR_IGRPMOD0 + i * 4);
+ }

/* Next redist */
gicr_ptr += 0x10000;
@@ -87,6 +93,10 @@ void gic_secure_init_primary(void)
raw_writel(~0x0, gicd_base + GICD_IGROUP0 + i * 4);
raw_writel(0x0, gicd_base + GICD_IGRPMOD0 + i * 4);
}
+ for (i = 0; i < ((typer >> 27) & GICD_TYPER_ITLineNumber); i++) {
+ raw_writel(~0x0, gicd_base + GICD_IGROUPR0E + i * 4);
+ raw_writel(0x0, gicd_base + GICD_IGRPMODR0E + i * 4);
+ }
}

void gic_secure_init(void)
--
2.18.0