[PATCH 1/3] dt-bindings: iommu: arm-smmu-v3: Allow PMU child nodes

Peng Fan (OSS)
2026-04-08T07:50:06Z

From: Peng Fan <peng.fan@nxp.com>

The Arm SMMU v3 specification defines an optional PMCG (Performance
Monitor Control Group) block. Per MMU-700 TRM, it has three 64KB pages,
with TCU Performance Monitor Counter Group (PMCG) registers starting at
offset 0x02000 in page 0. So PMCG could be described as a child node of the
SMMU in Devicetree.

Add a patternProperties entry to the arm,smmu-v3 binding to allow child
nodes matching "pmu@<addr>" and reference the existing
arm,smmu-v3-pmcg.yaml schema.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml | 10 ++++++++++
1 file changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
index 82957334bea24402b583e47eb61b5724c91e4378..1d09c5476e5f1a7c3e5c935b677641ee6cc9897e 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
@@ -50,6 +50,10 @@ properties:
- cmdq-sync # CMD_SYNC complete
- priq # PRI Queue not empty

+ '#address-cells': true
+ '#size-cells': true
+ ranges: true
+
'#iommu-cells':
const: 1

@@ -83,6 +87,12 @@ properties:
register access with page 0 offsets. Set for Cavium ThunderX2 silicon that
doesn't support SMMU page1 register space.

+patternProperties:
+ '^pmu@[0-9a-f]+$':
+ type: object
+ $ref: /schemas/perf/arm,smmu-v3-pmcg.yaml#
+ unevaluatedProperties: false
+
allOf:
- if:
not:

--
2.37.1