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Thu, 10 Sep 2026 16:17:29 -0700 From: Nicolin Chen To: , , , "Jonathan Cameron" CC: , , , , , , , Jean-Philippe Brucker , "Eric Auger" , , , , , , , , , Subject: [PATCH v4 07/15] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Date: Thu, 10 Sep 2026 16:16:59 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF000023CF:EE_|CH3PR12MB8996:EE_ X-MS-Office365-Filtering-Correlation-Id: e17ea611-56f1-4002-da05-08df0f91baf0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|82310400026|36860700016|376014|7416014|5023799004|11063799006|56012099006|10067099003|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: xzvrlbJZrK96Z0FQzvA2Y7DS9Vtpb/uwFnmUjUdmi5L2zOdNunO0Ji+dZtj2o9HKiRE2Bnan6+hfXcSj3v1sTv17cNB+APuhQUHlR4Q2/SDgYleydUZ8sNwf+wqSVkJM+G/CYFw3waUH1EpklmJZKOzeFO4h+6w5G40igsimQF978/j37c0MUcclD8K31LmW1ZOvd+3CG6ArFJR6ccB87AkRKYkcT8052sjLmagvRnTctcj6UlSABDE6zXCZwiza44G0SBXTu01vjoQdJlfB87Tuo1/DIZX7P+iS7Yh5P5WljhbAEJfYtX85uRXxcmcgan64OQmwRbBk6XmCFlC/TtRNC75R2Ph5lcS/PRIfjSBLS4NJVGwL3DnCMhLsIrbRpbHiwP8Ho+hcH+l2DB0d8WZbsuJOTu2YMRbDXOc9+P0HhWasS0Br9H+FpLx+0+Ici8lRYi/qgS4ZuPos2Nhk007AhCibqpywUxjEJAQKlcurCRM8BuiRKithxTndKQBizYNBWc5imDpaNGNu11NFmpo1B05q7DNa5dZGWx3CEqLI5czAqqxBULQ3zMPwwUmMlD569t/WI2NdsCO+rS9hXN6tw4VTDHdFemPLdikQ18AfBNdc+F7ED3kXSWuDZ8jT2ZHF124LRi28XVD1K0GFFQK5lkedqS6VeyaqtMkoCGjr1E4NzajYdGIVVbadNZ3Iq9RndofwvLRibnWncbAmpw== X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(1800799024)(82310400026)(36860700016)(376014)(7416014)(5023799004)(11063799006)(56012099006)(10067099003)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: wl54l9SEizUZgmsf9OAUDL3gQx3rmE6fRMfOdEjVB0S2iT7OYtPvwkFwlMToiKg+HAEvq1nzc2AvRgIRp4WGqhRJlZzw6uuOvCde5aTbK+C37McsEl+KcIJZV2XenSRqRfHLPuuq3i/MwUzo+UIEpxQyuagrx+IBzTbzXVjCop9I1rzfee14HyofIj80K5kCRNPaSyg/pGxZcvKHyYqiJJGkwZxisj1m8K6WoIg408gjgLmIk5V0Hd3PX/ZFfyIz0kVD/gRPtqv/ZNKqBgqU85el7NW/wvyC+dp7hh3LIVAGoOP9LnoR17J5Jzct1zmRJJZJssjnmYqfhLvz74FpAjjD0L0BpFacZKRfOcQLaO7/+/4Rr7J/E3yTJYkLwRwZnPQlEPniaXUyMVYXax75QH9LUNyKy/m0OYX/NTfMHg6sb/yyWDXYJwbWK9kQVxXM X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Sep 2026 23:17:49.0652 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e17ea611-56f1-4002-da05-08df0f91baf0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CF.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8996 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260910_161758_817535_0AF1A053 X-CRM114-Status: GOOD ( 19.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Malak Marrid To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() must issue a CMDQ_OP_PRI_RESP back to the SMMU. Both EVTQ stall events and PRIQ requests reach the IOPF layer with the same IOMMU_FAULT_PAGE_REQ, but these two fault models are mutually exclusive. A stalling master holds a transaction until CMDQ_OP_RESUME and has no reason to send a page request. A later patch rejects PRI for such a master, so the response command can be selected from stall_enabled or pri_enabled. Note that a CMD_PRI_RESP.Resp encodes 0b00 as ResponseFailure (a permanent non-paging error), 0b01 as InvalidRequest (page-in unsuccessful), and 0b10 as Success. So IOMMU_PAGE_RESP_FAILURE maps to PRI_RESP_DENY (0b00) while IOMMU_PAGE_RESP_INVALID maps to PRI_RESP_FAIL (0b01), following the codes rather than the similarity of the enum names. Extend arm_smmu_enable_iopf() to also proceed for a PRI-enabled master, so that attaching a fault-capable domain would set up IOPF for it. Note that a later change will set master->pri_enabled, once all PRI paths are ready. Note: streams[0].id remains the RID because arm_smmu_enable_iopf() rejects num_streams != 1. Co-developed-by: Barak Biber Signed-off-by: Barak Biber Co-developed-by: Stefan Kaestle Signed-off-by: Stefan Kaestle Signed-off-by: Malak Marrid Reviewed-by: Jonathan Cameron Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 74 +++++++++++++++------ 2 files changed, 56 insertions(+), 19 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 21b00b9296b31..558ba40f2f456 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1017,6 +1017,7 @@ struct arm_smmu_master { /* Locked by the iommu core using the group mutex */ struct arm_smmu_ctx_desc_cfg cd_table; unsigned int num_streams; + bool pri_enabled : 1; bool ats_enabled : 1; bool ste_ats_enabled : 1; bool stall_enabled; diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 8b7d88d469198..815847c2d7b43 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -1031,32 +1031,68 @@ static int arm_smmu_wait_for_queue_drained(struct arm_smmu_device *smmu, return -ETIMEDOUT; } -static void arm_smmu_page_response(struct device *dev, struct iopf_fault *unused, +static void arm_smmu_page_response(struct device *dev, struct iopf_fault *evt, struct iommu_page_response *resp) { struct arm_smmu_master *master = dev_iommu_priv_get(dev); - u8 resume_resp; + struct arm_smmu_cmd cmd; + int sid; - if (WARN_ON(!master->stall_enabled)) + if (WARN_ON_ONCE(evt->fault.type != IOMMU_FAULT_PAGE_REQ)) return; - switch (resp->code) { - case IOMMU_PAGE_RESP_INVALID: - case IOMMU_PAGE_RESP_FAILURE: - resume_resp = CMDQ_RESUME_0_RESP_ABORT; - break; - case IOMMU_PAGE_RESP_SUCCESS: - resume_resp = CMDQ_RESUME_0_RESP_RETRY; - break; - default: - resume_resp = CMDQ_RESUME_0_RESP_TERM; - break; + /* IOPF is gated to num_streams == 1 in arm_smmu_enable_iopf() */ + sid = master->streams[0].id; + + if (master->stall_enabled) { + u8 resume_resp; + + switch (resp->code) { + case IOMMU_PAGE_RESP_INVALID: + case IOMMU_PAGE_RESP_FAILURE: + resume_resp = CMDQ_RESUME_0_RESP_ABORT; + break; + case IOMMU_PAGE_RESP_SUCCESS: + resume_resp = CMDQ_RESUME_0_RESP_RETRY; + break; + default: + resume_resp = CMDQ_RESUME_0_RESP_TERM; + break; + } + cmd = arm_smmu_make_cmd_resume(sid, resp->grpid, resume_resp); + } else if (master->pri_enabled) { + struct iommu_fault_page_request *prm = &evt->fault.prm; + enum pri_resp pri_resp; + bool ssv; + + /* PCIe allows only one PRG Response per group */ + if (!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_LAST_PAGE)) + return; + switch (resp->code) { + case IOMMU_PAGE_RESP_SUCCESS: + pri_resp = PRI_RESP_SUCC; + break; + case IOMMU_PAGE_RESP_FAILURE: + /* 0b00 ResponseFailure: a permanent non-paging error */ + pri_resp = PRI_RESP_DENY; + break; + case IOMMU_PAGE_RESP_INVALID: + /* 0b01 InvalidRequest: page-in unsuccessful */ + pri_resp = PRI_RESP_FAIL; + break; + default: + WARN_ON(true); + return; + } + ssv = !!(prm->flags & IOMMU_FAULT_PAGE_REQUEST_PASID_VALID); + cmd = arm_smmu_make_cmd_pri_resp(sid, resp->pasid, ssv, + resp->grpid, pri_resp); + } else { + WARN_ON_ONCE(1); + return; } - arm_smmu_cmdq_issue_cmd(master->smmu, - arm_smmu_make_cmd_resume(master->streams[0].id, - resp->grpid, - resume_resp)); + arm_smmu_cmdq_issue_cmd(master->smmu, cmd); /* * Don't send a SYNC, it doesn't do anything for RESUME or PRI_RESP. * RESUME consumption guarantees that the stalled transaction will be @@ -3212,7 +3248,7 @@ static int arm_smmu_enable_iopf(struct arm_smmu_master *master, * device-specific fault handlers and don't need IOPF, so this is not a * failure. */ - if (!master->stall_enabled) + if (!master->stall_enabled && !master->pri_enabled) return 0; /* We're not keeping track of SIDs in fault events */ -- 2.43.0