From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 13275C433DB for ; Wed, 3 Feb 2021 10:38:21 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C24C964E0A for ; Wed, 3 Feb 2021 10:38:20 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C24C964E0A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Type: Content-Transfer-Encoding:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:Message-ID:References:In-Reply-To:Subject:To:From: Date:MIME-Version:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=48jt2Fy7hBttIMHc3wpIwKrEXOC+N4bpQdGzDQxHVPY=; b=Q+DHUUqEATs3q8upZajFmGEtO 2OMYjydJNuemklJapMFLaO0qcy++xZVDRFL8VEPt2BG3N2FhHK/WQDGldhXzGoESvlyV31koua11K CgEMD9RmJfQ/Ikrz5hfVe5xwuzSZhC02sVaBW65+M+uSMWLf3DYitNhPh8U8A3XSrRaj5n1X6D3EI tf5ubC5fi11zfQMV7FAg256CPSi64AGBaXhVSjIx225WvngzO+Y8Z3L9QJ7z/VpCNrmYtVngNidnf 5h+KnE+xSJslzIMC3lPH57UbuZeCVHowiF2hlobLYWKXCuJb42xaX964mbcpOfhKOmFFN5EHSrHV+ 4apKBnycg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7FWz-0004zp-6i; Wed, 03 Feb 2021 10:37:05 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1l7FWw-0004yb-D8 for linux-arm-kernel@lists.infradead.org; Wed, 03 Feb 2021 10:37:03 +0000 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 6732264E0A; Wed, 3 Feb 2021 10:37:01 +0000 (UTC) Received: from disco-boy.misterjones.org ([51.254.78.96] helo=www.loen.fr) by disco-boy.misterjones.org with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (Exim 4.94) (envelope-from ) id 1l7FWt-00Bj62-28; Wed, 03 Feb 2021 10:36:59 +0000 MIME-Version: 1.0 Date: Wed, 03 Feb 2021 10:36:59 +0000 From: Marc Zyngier To: Auger Eric Subject: Re: [PATCH v2 6/7] KVM: arm64: Upgrade PMU support to ARMv8.4 In-Reply-To: <56041147-0bd8-dbb2-d1ca-550f3db7f05d@redhat.com> References: <20210125122638.2947058-1-maz@kernel.org> <20210125122638.2947058-7-maz@kernel.org> <56041147-0bd8-dbb2-d1ca-550f3db7f05d@redhat.com> User-Agent: Roundcube Webmail/1.4.10 Message-ID: X-Sender: maz@kernel.org X-SA-Exim-Connect-IP: 51.254.78.96 X-SA-Exim-Rcpt-To: eric.auger@redhat.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, alexandru.elisei@arm.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210203_053702_659023_EEB73C83 X-CRM114-Status: GOOD ( 22.10 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Suzuki K Poulose , kernel-team@android.com, James Morse , linux-arm-kernel@lists.infradead.org, Alexandru Elisei , kvmarm@lists.cs.columbia.edu, Julien Thierry Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Eric, On 2021-01-27 17:53, Auger Eric wrote: > Hi Marc, > > On 1/25/21 1:26 PM, Marc Zyngier wrote: >> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be >> pretty easy. All that is required is support for PMMIR_EL1, which >> is read-only, and for which returning 0 is a valid option as long >> as we don't advertise STALL_SLOT as an implemented event. >> >> Let's just do that and adjust what we return to the guest. >> >> Signed-off-by: Marc Zyngier >> --- >> arch/arm64/include/asm/sysreg.h | 3 +++ >> arch/arm64/kvm/pmu-emul.c | 6 ++++++ >> arch/arm64/kvm/sys_regs.c | 11 +++++++---- >> 3 files changed, 16 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm64/include/asm/sysreg.h >> b/arch/arm64/include/asm/sysreg.h >> index 8b5e7e5c3cc8..2fb3f386588c 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -846,7 +846,10 @@ >> >> #define ID_DFR0_PERFMON_SHIFT 24 >> >> +#define ID_DFR0_PERFMON_8_0 0x3 >> #define ID_DFR0_PERFMON_8_1 0x4 >> +#define ID_DFR0_PERFMON_8_4 0x5 >> +#define ID_DFR0_PERFMON_8_5 0x6 >> >> #define ID_ISAR4_SWP_FRAC_SHIFT 28 >> #define ID_ISAR4_PSR_M_SHIFT 24 >> diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c >> index 398f6df1bbe4..72cd704a8368 100644 >> --- a/arch/arm64/kvm/pmu-emul.c >> +++ b/arch/arm64/kvm/pmu-emul.c >> @@ -795,6 +795,12 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, >> bool pmceid1) >> base = 0; >> } else { >> val = read_sysreg(pmceid1_el0); >> + /* >> + * Don't advertise STALL_SLOT, as PMMIR_EL0 is handled >> + * as RAZ >> + */ >> + if (vcpu->kvm->arch.pmuver >= ID_AA64DFR0_PMUVER_8_4) >> + val &= ~BIT_ULL(ARMV8_PMUV3_PERFCTR_STALL_SLOT - 32); > what about the STALL_SLOT_BACKEND and FRONTEND events then? Aren't these a mandatory ARMv8.1 feature? I don't see a reason to drop them. >> base = 32; >> } >> >> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >> index 8f79ec1fffa7..5da536ab738d 100644 >> --- a/arch/arm64/kvm/sys_regs.c >> +++ b/arch/arm64/kvm/sys_regs.c >> @@ -1051,16 +1051,16 @@ static u64 read_id_reg(const struct kvm_vcpu >> *vcpu, >> /* Limit debug to ARMv8.0 */ >> val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); >> val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); >> - /* Limit guests to PMUv3 for ARMv8.1 */ >> + /* Limit guests to PMUv3 for ARMv8.4 */ >> val = cpuid_feature_cap_perfmon_field(val, >> ID_AA64DFR0_PMUVER_SHIFT, >> - kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_1 : 0); >> + kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0); >> break; >> case SYS_ID_DFR0_EL1: >> - /* Limit guests to PMUv3 for ARMv8.1 */ >> + /* Limit guests to PMUv3 for ARMv8.4 */ >> val = cpuid_feature_cap_perfmon_field(val, >> ID_DFR0_PERFMON_SHIFT, >> - kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_1 : 0); >> + kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0); >> break; >> } >> >> @@ -1496,6 +1496,7 @@ static const struct sys_reg_desc sys_reg_descs[] >> = { >> >> { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, >> PMINTENSET_EL1 }, >> { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, >> PMINTENSET_EL1 }, > "KVM: arm64: Hide PMU registers from userspace when not available" > changed the above, doesn't it? Yes, that's because the fix didn't make it in mainline before 5.11-rc5, and I based this on -rc4. I'll fix it at merge time. Thanks, M. -- Jazz is not dead. It just smells funny... _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel