From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 797E2C77B73 for ; Mon, 5 Jun 2023 12:38:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:From:References:CC:To:Subject: MIME-Version:Date:Message-ID:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=HLAAJj1DJk+8g51k8KGZJZdJl4GjneiUGOm2odKwoJo=; b=4407dHS90Ib1NO lX04vwFXFHDDtRxmHyxi0WtlCV7zYCVpk0E8PzZNh6DaNJE2jQgZtDSHl66WmynJsAMH/QHRGKh1D 1YjIRi0dDX4+2MguE9rX2KeTGaaG7e8m5UlZyRjH/KXQkg6MyXkdJuTR8tm3glWX7ZnBfHzzkqS7i XAWynaRn+a5W94iID3hix5brTDG1Pg+BQdwoqZm9xGXGDfQACwcfWTef0E7oe90WB04itO8QPG1OV vkb45DlPx+zjoT2dn95CPtyIP54mGL7inMcd9/3FuZnrKBhgM+NogLN+ZTRuEJ09egEFZRtOHgzjO Wul1juKFpDzW8rGP8bpA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1q69St-00FTKw-2a; Mon, 05 Jun 2023 12:37:39 +0000 Received: from esa.microchip.iphmx.com ([68.232.153.233]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1q69Sq-00FTK7-1W for linux-arm-kernel@lists.infradead.org; Mon, 05 Jun 2023 12:37:38 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685968657; x=1717504657; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=3qZ9HUtKkrRCZ6pttiD0fABhp7XxMD/NZypAKra7/nI=; b=t3rzslJhw9DaGhBrrdqlbcrvoxLNy3ZkkDrteRAIn0Db9DDsA1ZnIDuN MKnzWF9wJZ7RVtkT8uxGMkZ653ZjFK1kKHwT6zza0fjUe1AMGElYv13Uh 6hcje6plBAg90Ct/3s4gsIHHgiIw1F5F8yK5wBpkk4MeVtARs2Igy+Vfv hfvBa2FHgKIIjYYvEb5o35NwIDjcFB6c/YWX4qbbf9M/sApy1p3by9zhW b/8a17iT56eKCnXKvrFzZi2lcWm6h98un2zXf4ybMCAJvk9GDVqGoJv5+ IAXCMfAG7Nn0rouud+4JabjkwdZHoHq6mCxBqAXbMchSj5KDFuYyJCN+C w==; X-IronPort-AV: E=Sophos;i="6.00,217,1681196400"; d="scan'208";a="216851473" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 05 Jun 2023 05:37:35 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Mon, 5 Jun 2023 05:37:29 -0700 Received: from [10.159.245.112] (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Mon, 5 Jun 2023 05:37:23 -0700 Message-ID: Date: Mon, 5 Jun 2023 14:37:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH 15/21] dt-bindings: irqchip/atmel-aic5: Add support for sam9x7 aic Content-Language: en-US To: Conor Dooley , Arnd Bergmann CC: Varshini Rajendran , Thomas Gleixner , Marc Zyngier , Rob Herring , , Conor Dooley , Alexandre Belloni , Claudiu Beznea , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Greg Kroah-Hartman , Russell King , "Michael Turquette" , Stephen Boyd , Sebastian Reichel , Mark Brown , "Gregory Clement" , Sudeep Holla , Balamanikandan Gunasundar , , , , , Netdev , , , , , , , , , , References: <20230603200243.243878-1-varshini.rajendran@microchip.com> <20230603200243.243878-16-varshini.rajendran@microchip.com> <20230603-fervor-kilowatt-662c84b94853@spud> <20230603-sanded-blunderer-73cdd7c290c1@spud> <4d3694b3-8728-42c1-8497-ae38134db37c@app.fastmail.com> <20230604-cohesive-unmoving-032da3272620@spud> From: Nicolas Ferre Organization: microchip In-Reply-To: <20230604-cohesive-unmoving-032da3272620@spud> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230605_053736_687571_B5CC1DB2 X-CRM114-Status: GOOD ( 27.55 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Arnd, Conor, On 04/06/2023 at 23:08, Conor Dooley wrote: > On Sun, Jun 04, 2023 at 11:49:48AM +0200, Arnd Bergmann wrote: >> On Sat, Jun 3, 2023, at 23:23, Conor Dooley wrote: >>> On Sat, Jun 03, 2023 at 10:19:50PM +0100, Conor Dooley wrote: >>>> Hey Varshini, >>>> >>>> On Sun, Jun 04, 2023 at 01:32:37AM +0530, Varshini Rajendran wrote: >>>>> Document the support added for the Advanced interrupt controller(AIC) >>>>> chip in the sam9x7 soc family >>>> Please do not add new family based compatibles, but rather use per-soc >>>> compatibles instead. >>> These things leave me penally confused. Afaiu, sam9x60 is a particular > s/penally/perennially/ > >>> SoC. sam9x7 is actually a family, containing sam9x70, sam9x72 and >>> sam9x75. It would appear to me that each should have its own compatible, >>> no? >> I think the usual way this works is that the sam9x7 refers to the >> SoC design as in what is actually part of the chip, whereas the 70, >> 72 and 75 models are variants that have a certain subset of the >> features enabled. Yes, That's the case. >> If that is the case here, then referring to the on-chip parts by >> the sam9x7 name makes sense, and this is similar to what we do >> on TI AM-series chips. This is what we did for most of our SoCs families, indeed. > If it is the case that what differentiates them is having bits chopped > off, and there's no implementation differences that seems fair. Ok, thanks. >> There is a remaining risk that a there would be a future >> sam9x71/73/74/76/... product based on a new chip that uses >> incompatible devices, but at that point we can still use the >> more specific model number to identify those without being >> ambiguous. This is exactly what we did for sama5d29 which is not the same silicon vs. the other members of the sama5d2 family. We used the more specify sama5d29 sub-string for describing the changing parts (CAN-FD and Ethernet). >> The same thing can of course happen when a SoC >> vendor reuses a specific name of a prior product with an update >> chip that has software visible changes. >> >> I'd just leave this up to Varshini and the other at91 maintainers >> here, provided they understand the exact risks. Yep, I understand the risk and will try to review the compatibility strings that would need more precise description (maybe PMC or AIC). > Ye, seems fair to me. Nicolas/Claudiu etc, is there a convention to use > the "0" model as the compatible (like the 9x60 did) or have "random" > things been done so far? sam9x60 was a single SoC, not a member of a "family", so there was no meaning of the "0" here. Moreover, the "0" ones are usually not the subset, if it even exists. So far, we used the silicon string to define the compatibility string, adding a more precise string for hardware of family members that needed it (as mentioned above for sama5d29). >> It's different for the parts that are listed as just sam9x60 >> compatible in the DT, I think those clearly need to have sam9x7 >> in the compatible list, but could have the sam9x60 identifier >> as a fallback if the hardware is compatible. > Aye. Yep, agreed. Thanks for your help. Best regards, Nicolas -- Nicolas Ferre _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel