* [PATCH v14 1/4] s390: Rename TIF_SINGLE_STEP to TIF_SINGLESTEP
2026-03-20 10:42 [PATCH v14 0/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
@ 2026-03-20 10:42 ` Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits Jinjie Ruan
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Jinjie Ruan @ 2026-03-20 10:42 UTC (permalink / raw)
To: catalin.marinas, will, chenhuacai, kernel, hca, gor, agordeev,
borntraeger, svens, oleg, tglx, mingo, bp, dave.hansen, hpa, arnd,
shuah, kevin.brodsky, ruanjinjie, yeoreum.yun, anshuman.khandual,
thuth, ryan.roberts, mark.rutland, song, ziyao, linusw,
schuster.simon, jremus, akpm, mathieu.desnoyers, kmal, dvyukov,
reddybalavignesh9979, x86, linux-arm-kernel, linux-kernel,
loongarch, linux-s390, linux-arch, linux-kselftest
Rename TIF_SINGLE_STEP to TIF_SINGLESTEP to align with the naming
convention used by arm64, x86, and other architectures.
By aligning the name, TIF_SINGLESTEP can be consolidated into the generic
TIF bits definitions, reducing architectural divergence and simplifying
cross-architecture entry/exit logic.
No functional changes intended.
Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Acked-by: Heiko Carstens <hca@linux.ibm.com>
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
arch/s390/include/asm/thread_info.h | 4 ++--
arch/s390/kernel/process.c | 2 +-
arch/s390/kernel/ptrace.c | 20 ++++++++++----------
arch/s390/kernel/signal.c | 6 +++---
4 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 6a548a819400..1bcd42614e41 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -69,7 +69,7 @@ void arch_setup_new_exec(void);
#define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */
#define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */
#define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */
-#define TIF_SINGLE_STEP 21 /* This task is single stepped */
+#define TIF_SINGLESTEP 21 /* This task is single stepped */
#define TIF_BLOCK_STEP 22 /* This task is block stepped */
#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */
@@ -77,7 +77,7 @@ void arch_setup_new_exec(void);
#define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE)
#define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST)
#define _TIF_PER_TRAP BIT(TIF_PER_TRAP)
-#define _TIF_SINGLE_STEP BIT(TIF_SINGLE_STEP)
+#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
#define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP)
#define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP)
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index 0df95dcb2101..3accc0c064a0 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -122,7 +122,7 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args)
/* Don't copy debug registers */
memset(&p->thread.per_user, 0, sizeof(p->thread.per_user));
memset(&p->thread.per_event, 0, sizeof(p->thread.per_event));
- clear_tsk_thread_flag(p, TIF_SINGLE_STEP);
+ clear_tsk_thread_flag(p, TIF_SINGLESTEP);
p->thread.per_flags = 0;
/* Initialize per thread user and system timer values */
p->thread.user_timer = 0;
diff --git a/arch/s390/kernel/ptrace.c b/arch/s390/kernel/ptrace.c
index 125ca4c4e30c..d2cf91f4ac3f 100644
--- a/arch/s390/kernel/ptrace.c
+++ b/arch/s390/kernel/ptrace.c
@@ -90,8 +90,8 @@ void update_cr_regs(struct task_struct *task)
new.start.val = thread->per_user.start;
new.end.val = thread->per_user.end;
- /* merge TIF_SINGLE_STEP into user specified PER registers. */
- if (test_tsk_thread_flag(task, TIF_SINGLE_STEP) ||
+ /* merge TIF_SINGLESTEP into user specified PER registers. */
+ if (test_tsk_thread_flag(task, TIF_SINGLESTEP) ||
test_tsk_thread_flag(task, TIF_UPROBE_SINGLESTEP)) {
if (test_tsk_thread_flag(task, TIF_BLOCK_STEP))
new.control.val |= PER_EVENT_BRANCH;
@@ -119,18 +119,18 @@ void update_cr_regs(struct task_struct *task)
void user_enable_single_step(struct task_struct *task)
{
clear_tsk_thread_flag(task, TIF_BLOCK_STEP);
- set_tsk_thread_flag(task, TIF_SINGLE_STEP);
+ set_tsk_thread_flag(task, TIF_SINGLESTEP);
}
void user_disable_single_step(struct task_struct *task)
{
clear_tsk_thread_flag(task, TIF_BLOCK_STEP);
- clear_tsk_thread_flag(task, TIF_SINGLE_STEP);
+ clear_tsk_thread_flag(task, TIF_SINGLESTEP);
}
void user_enable_block_step(struct task_struct *task)
{
- set_tsk_thread_flag(task, TIF_SINGLE_STEP);
+ set_tsk_thread_flag(task, TIF_SINGLESTEP);
set_tsk_thread_flag(task, TIF_BLOCK_STEP);
}
@@ -143,7 +143,7 @@ void ptrace_disable(struct task_struct *task)
{
memset(&task->thread.per_user, 0, sizeof(task->thread.per_user));
memset(&task->thread.per_event, 0, sizeof(task->thread.per_event));
- clear_tsk_thread_flag(task, TIF_SINGLE_STEP);
+ clear_tsk_thread_flag(task, TIF_SINGLESTEP);
clear_tsk_thread_flag(task, TIF_PER_TRAP);
task->thread.per_flags = 0;
}
@@ -155,19 +155,19 @@ static inline unsigned long __peek_user_per(struct task_struct *child,
{
if (addr == offsetof(struct per_struct_kernel, cr9))
/* Control bits of the active per set. */
- return test_thread_flag(TIF_SINGLE_STEP) ?
+ return test_thread_flag(TIF_SINGLESTEP) ?
PER_EVENT_IFETCH : child->thread.per_user.control;
else if (addr == offsetof(struct per_struct_kernel, cr10))
/* Start address of the active per set. */
- return test_thread_flag(TIF_SINGLE_STEP) ?
+ return test_thread_flag(TIF_SINGLESTEP) ?
0 : child->thread.per_user.start;
else if (addr == offsetof(struct per_struct_kernel, cr11))
/* End address of the active per set. */
- return test_thread_flag(TIF_SINGLE_STEP) ?
+ return test_thread_flag(TIF_SINGLESTEP) ?
-1UL : child->thread.per_user.end;
else if (addr == offsetof(struct per_struct_kernel, bits))
/* Single-step bit. */
- return test_thread_flag(TIF_SINGLE_STEP) ?
+ return test_thread_flag(TIF_SINGLESTEP) ?
(1UL << (BITS_PER_LONG - 1)) : 0;
else if (addr == offsetof(struct per_struct_kernel, starting_addr))
/* Start address of the user specified per set. */
diff --git a/arch/s390/kernel/signal.c b/arch/s390/kernel/signal.c
index 4874de5edea0..83f7650f2032 100644
--- a/arch/s390/kernel/signal.c
+++ b/arch/s390/kernel/signal.c
@@ -423,7 +423,7 @@ static void handle_signal(struct ksignal *ksig, sigset_t *oldset,
else
ret = setup_frame(ksig->sig, &ksig->ka, oldset, regs);
- signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLE_STEP));
+ signal_setup_done(ret, ksig, test_thread_flag(TIF_SINGLESTEP));
}
/*
@@ -491,7 +491,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs)
regs->gprs[2] = regs->orig_gpr2;
current->restart_block.arch_data = regs->psw.addr;
regs->psw.addr = VDSO_SYMBOL(current, restart_syscall);
- if (test_thread_flag(TIF_SINGLE_STEP))
+ if (test_thread_flag(TIF_SINGLESTEP))
clear_thread_flag(TIF_PER_TRAP);
break;
case -ERESTARTNOHAND:
@@ -499,7 +499,7 @@ void arch_do_signal_or_restart(struct pt_regs *regs)
case -ERESTARTNOINTR:
regs->gprs[2] = regs->orig_gpr2;
regs->psw.addr = __rewind_psw(regs->psw, regs->int_code >> 16);
- if (test_thread_flag(TIF_SINGLE_STEP))
+ if (test_thread_flag(TIF_SINGLESTEP))
clear_thread_flag(TIF_PER_TRAP);
break;
}
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits
2026-03-20 10:42 [PATCH v14 0/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 1/4] s390: Rename TIF_SINGLE_STEP to TIF_SINGLESTEP Jinjie Ruan
@ 2026-03-20 10:42 ` Jinjie Ruan
2026-04-09 7:42 ` Mark Rutland
2026-03-20 10:42 ` [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 4/4] selftests: sud_test: Support aarch64 Jinjie Ruan
3 siblings, 1 reply; 9+ messages in thread
From: Jinjie Ruan @ 2026-03-20 10:42 UTC (permalink / raw)
To: catalin.marinas, will, chenhuacai, kernel, hca, gor, agordeev,
borntraeger, svens, oleg, tglx, mingo, bp, dave.hansen, hpa, arnd,
shuah, kevin.brodsky, ruanjinjie, yeoreum.yun, anshuman.khandual,
thuth, ryan.roberts, mark.rutland, song, ziyao, linusw,
schuster.simon, jremus, akpm, mathieu.desnoyers, kmal, dvyukov,
reddybalavignesh9979, x86, linux-arm-kernel, linux-kernel,
loongarch, linux-s390, linux-arch, linux-kselftest
Currently, x86, ARM64, s390, and LoongArch all define and use
TIF_SINGLESTEP to track single-stepping state.
Since this flag is shared across multiple major architectures and serves
a common purpose in the generic entry/exit paths, move TIF_SINGLESTEP
into the generic Thread Information Flags (TIF) infrastructure.
This consolidation reduces architecture-specific boilerplate code and
ensures consistency for generic features that rely on single-step
state tracking.
Cc: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Acked-by: Heiko Carstens <hca@linux.ibm.com> # s390
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
arch/loongarch/include/asm/thread_info.h | 11 +++++------
arch/s390/include/asm/thread_info.h | 7 +++----
arch/x86/include/asm/thread_info.h | 6 ++----
include/asm-generic/thread_info_tif.h | 5 +++++
4 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/arch/loongarch/include/asm/thread_info.h b/arch/loongarch/include/asm/thread_info.h
index 4d7117fcdc78..a2ec87f18e1d 100644
--- a/arch/loongarch/include/asm/thread_info.h
+++ b/arch/loongarch/include/asm/thread_info.h
@@ -70,6 +70,7 @@ register unsigned long current_stack_pointer __asm__("$sp");
*/
#define HAVE_TIF_NEED_RESCHED_LAZY
#define HAVE_TIF_RESTORE_SIGMASK
+#define HAVE_TIF_SINGLESTEP
#include <asm-generic/thread_info_tif.h>
@@ -82,11 +83,10 @@ register unsigned long current_stack_pointer __asm__("$sp");
#define TIF_32BIT_REGS 21 /* 32-bit general purpose registers */
#define TIF_32BIT_ADDR 22 /* 32-bit address space */
#define TIF_LOAD_WATCH 23 /* If set, load watch registers */
-#define TIF_SINGLESTEP 24 /* Single Step */
-#define TIF_LSX_CTX_LIVE 25 /* LSX context must be preserved */
-#define TIF_LASX_CTX_LIVE 26 /* LASX context must be preserved */
-#define TIF_USEDLBT 27 /* LBT was used by this task this quantum (SMP) */
-#define TIF_LBT_CTX_LIVE 28 /* LBT context must be preserved */
+#define TIF_LSX_CTX_LIVE 24 /* LSX context must be preserved */
+#define TIF_LASX_CTX_LIVE 25 /* LASX context must be preserved */
+#define TIF_USEDLBT 26 /* LBT was used by this task this quantum (SMP) */
+#define TIF_LBT_CTX_LIVE 27 /* LBT context must be preserved */
#define _TIF_NOHZ BIT(TIF_NOHZ)
#define _TIF_USEDFPU BIT(TIF_USEDFPU)
@@ -96,7 +96,6 @@ register unsigned long current_stack_pointer __asm__("$sp");
#define _TIF_32BIT_REGS BIT(TIF_32BIT_REGS)
#define _TIF_32BIT_ADDR BIT(TIF_32BIT_ADDR)
#define _TIF_LOAD_WATCH BIT(TIF_LOAD_WATCH)
-#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
#define _TIF_LSX_CTX_LIVE BIT(TIF_LSX_CTX_LIVE)
#define _TIF_LASX_CTX_LIVE BIT(TIF_LASX_CTX_LIVE)
#define _TIF_USEDLBT BIT(TIF_USEDLBT)
diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
index 1bcd42614e41..95be5258a422 100644
--- a/arch/s390/include/asm/thread_info.h
+++ b/arch/s390/include/asm/thread_info.h
@@ -61,6 +61,7 @@ void arch_setup_new_exec(void);
*/
#define HAVE_TIF_NEED_RESCHED_LAZY
#define HAVE_TIF_RESTORE_SIGMASK
+#define HAVE_TIF_SINGLESTEP
#include <asm-generic/thread_info_tif.h>
@@ -69,15 +70,13 @@ void arch_setup_new_exec(void);
#define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */
#define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */
#define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */
-#define TIF_SINGLESTEP 21 /* This task is single stepped */
-#define TIF_BLOCK_STEP 22 /* This task is block stepped */
-#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */
+#define TIF_BLOCK_STEP 20 /* This task is block stepped */
+#define TIF_UPROBE_SINGLESTEP 21 /* This task is uprobe single stepped */
#define _TIF_ASCE_PRIMARY BIT(TIF_ASCE_PRIMARY)
#define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE)
#define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST)
#define _TIF_PER_TRAP BIT(TIF_PER_TRAP)
-#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
#define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP)
#define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP)
diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
index 0067684afb5b..f59072ba1473 100644
--- a/arch/x86/include/asm/thread_info.h
+++ b/arch/x86/include/asm/thread_info.h
@@ -98,9 +98,8 @@ struct thread_info {
#define TIF_IO_BITMAP 22 /* uses I/O bitmap */
#define TIF_SPEC_FORCE_UPDATE 23 /* Force speculation MSR update in context switch */
#define TIF_FORCED_TF 24 /* true if TF in eflags artificially */
-#define TIF_SINGLESTEP 25 /* reenable singlestep on user return*/
-#define TIF_BLOCKSTEP 26 /* set when we want DEBUGCTLMSR_BTF */
-#define TIF_ADDR32 27 /* 32-bit address space on 64 bits */
+#define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */
+#define TIF_ADDR32 26 /* 32-bit address space on 64 bits */
#define _TIF_SSBD BIT(TIF_SSBD)
#define _TIF_SPEC_IB BIT(TIF_SPEC_IB)
@@ -112,7 +111,6 @@ struct thread_info {
#define _TIF_SPEC_FORCE_UPDATE BIT(TIF_SPEC_FORCE_UPDATE)
#define _TIF_FORCED_TF BIT(TIF_FORCED_TF)
#define _TIF_BLOCKSTEP BIT(TIF_BLOCKSTEP)
-#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
#define _TIF_ADDR32 BIT(TIF_ADDR32)
/* flags to check in __switch_to() */
diff --git a/include/asm-generic/thread_info_tif.h b/include/asm-generic/thread_info_tif.h
index da1610a78f92..b277fe06aee3 100644
--- a/include/asm-generic/thread_info_tif.h
+++ b/include/asm-generic/thread_info_tif.h
@@ -48,4 +48,9 @@
#define TIF_RSEQ 11 // Run RSEQ fast path
#define _TIF_RSEQ BIT(TIF_RSEQ)
+#ifdef HAVE_TIF_SINGLESTEP
+#define TIF_SINGLESTEP 12 /* reenable singlestep on user return*/
+#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
+#endif
+
#endif /* _ASM_GENERIC_THREAD_INFO_TIF_H_ */
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits
2026-03-20 10:42 ` [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits Jinjie Ruan
@ 2026-04-09 7:42 ` Mark Rutland
0 siblings, 0 replies; 9+ messages in thread
From: Mark Rutland @ 2026-04-09 7:42 UTC (permalink / raw)
To: Jinjie Ruan
Cc: catalin.marinas, will, chenhuacai, kernel, hca, gor, agordeev,
borntraeger, svens, oleg, tglx, mingo, bp, dave.hansen, hpa, arnd,
shuah, kevin.brodsky, yeoreum.yun, anshuman.khandual, thuth,
ryan.roberts, song, ziyao, linusw, schuster.simon, jremus, akpm,
mathieu.desnoyers, kmal, dvyukov, reddybalavignesh9979, x86,
linux-arm-kernel, linux-kernel, loongarch, linux-s390, linux-arch,
linux-kselftest
On Fri, Mar 20, 2026 at 06:42:20PM +0800, Jinjie Ruan wrote:
> Currently, x86, ARM64, s390, and LoongArch all define and use
> TIF_SINGLESTEP to track single-stepping state.
Do the architectures actually use the flag in the same way?
I'd expect that this is used subtly differently across those
architectures, and so isn't necessarily generic.
> Since this flag is shared across multiple major architectures and serves
> a common purpose in the generic entry/exit paths, move TIF_SINGLESTEP
> into the generic Thread Information Flags (TIF) infrastructure.
>
> This consolidation reduces architecture-specific boilerplate code and
> ensures consistency for generic features that rely on single-step
> state tracking.
Is it necessary to make this generic in order to move to generic irq
flags? I'd expect that generic code cannot make use of this due to the
different semantics across architectures, as noted abobve.
I think it's probably better to keep this architecture-specific for now,
where architectures can clearly define how they're using this bit.
Am I missing some reason why it's necessary to make this generic?
Mark.
> Cc: Thomas Gleixner <tglx@kernel.org>
> Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
> Reviewed-by: Linus Walleij <linusw@kernel.org>
> Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
> Acked-by: Heiko Carstens <hca@linux.ibm.com> # s390
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
> ---
> arch/loongarch/include/asm/thread_info.h | 11 +++++------
> arch/s390/include/asm/thread_info.h | 7 +++----
> arch/x86/include/asm/thread_info.h | 6 ++----
> include/asm-generic/thread_info_tif.h | 5 +++++
> 4 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/thread_info.h b/arch/loongarch/include/asm/thread_info.h
> index 4d7117fcdc78..a2ec87f18e1d 100644
> --- a/arch/loongarch/include/asm/thread_info.h
> +++ b/arch/loongarch/include/asm/thread_info.h
> @@ -70,6 +70,7 @@ register unsigned long current_stack_pointer __asm__("$sp");
> */
> #define HAVE_TIF_NEED_RESCHED_LAZY
> #define HAVE_TIF_RESTORE_SIGMASK
> +#define HAVE_TIF_SINGLESTEP
>
> #include <asm-generic/thread_info_tif.h>
>
> @@ -82,11 +83,10 @@ register unsigned long current_stack_pointer __asm__("$sp");
> #define TIF_32BIT_REGS 21 /* 32-bit general purpose registers */
> #define TIF_32BIT_ADDR 22 /* 32-bit address space */
> #define TIF_LOAD_WATCH 23 /* If set, load watch registers */
> -#define TIF_SINGLESTEP 24 /* Single Step */
> -#define TIF_LSX_CTX_LIVE 25 /* LSX context must be preserved */
> -#define TIF_LASX_CTX_LIVE 26 /* LASX context must be preserved */
> -#define TIF_USEDLBT 27 /* LBT was used by this task this quantum (SMP) */
> -#define TIF_LBT_CTX_LIVE 28 /* LBT context must be preserved */
> +#define TIF_LSX_CTX_LIVE 24 /* LSX context must be preserved */
> +#define TIF_LASX_CTX_LIVE 25 /* LASX context must be preserved */
> +#define TIF_USEDLBT 26 /* LBT was used by this task this quantum (SMP) */
> +#define TIF_LBT_CTX_LIVE 27 /* LBT context must be preserved */
>
> #define _TIF_NOHZ BIT(TIF_NOHZ)
> #define _TIF_USEDFPU BIT(TIF_USEDFPU)
> @@ -96,7 +96,6 @@ register unsigned long current_stack_pointer __asm__("$sp");
> #define _TIF_32BIT_REGS BIT(TIF_32BIT_REGS)
> #define _TIF_32BIT_ADDR BIT(TIF_32BIT_ADDR)
> #define _TIF_LOAD_WATCH BIT(TIF_LOAD_WATCH)
> -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
> #define _TIF_LSX_CTX_LIVE BIT(TIF_LSX_CTX_LIVE)
> #define _TIF_LASX_CTX_LIVE BIT(TIF_LASX_CTX_LIVE)
> #define _TIF_USEDLBT BIT(TIF_USEDLBT)
> diff --git a/arch/s390/include/asm/thread_info.h b/arch/s390/include/asm/thread_info.h
> index 1bcd42614e41..95be5258a422 100644
> --- a/arch/s390/include/asm/thread_info.h
> +++ b/arch/s390/include/asm/thread_info.h
> @@ -61,6 +61,7 @@ void arch_setup_new_exec(void);
> */
> #define HAVE_TIF_NEED_RESCHED_LAZY
> #define HAVE_TIF_RESTORE_SIGMASK
> +#define HAVE_TIF_SINGLESTEP
>
> #include <asm-generic/thread_info_tif.h>
>
> @@ -69,15 +70,13 @@ void arch_setup_new_exec(void);
> #define TIF_GUARDED_STORAGE 17 /* load guarded storage control block */
> #define TIF_ISOLATE_BP_GUEST 18 /* Run KVM guests with isolated BP */
> #define TIF_PER_TRAP 19 /* Need to handle PER trap on exit to usermode */
> -#define TIF_SINGLESTEP 21 /* This task is single stepped */
> -#define TIF_BLOCK_STEP 22 /* This task is block stepped */
> -#define TIF_UPROBE_SINGLESTEP 23 /* This task is uprobe single stepped */
> +#define TIF_BLOCK_STEP 20 /* This task is block stepped */
> +#define TIF_UPROBE_SINGLESTEP 21 /* This task is uprobe single stepped */
>
> #define _TIF_ASCE_PRIMARY BIT(TIF_ASCE_PRIMARY)
> #define _TIF_GUARDED_STORAGE BIT(TIF_GUARDED_STORAGE)
> #define _TIF_ISOLATE_BP_GUEST BIT(TIF_ISOLATE_BP_GUEST)
> #define _TIF_PER_TRAP BIT(TIF_PER_TRAP)
> -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
> #define _TIF_BLOCK_STEP BIT(TIF_BLOCK_STEP)
> #define _TIF_UPROBE_SINGLESTEP BIT(TIF_UPROBE_SINGLESTEP)
>
> diff --git a/arch/x86/include/asm/thread_info.h b/arch/x86/include/asm/thread_info.h
> index 0067684afb5b..f59072ba1473 100644
> --- a/arch/x86/include/asm/thread_info.h
> +++ b/arch/x86/include/asm/thread_info.h
> @@ -98,9 +98,8 @@ struct thread_info {
> #define TIF_IO_BITMAP 22 /* uses I/O bitmap */
> #define TIF_SPEC_FORCE_UPDATE 23 /* Force speculation MSR update in context switch */
> #define TIF_FORCED_TF 24 /* true if TF in eflags artificially */
> -#define TIF_SINGLESTEP 25 /* reenable singlestep on user return*/
> -#define TIF_BLOCKSTEP 26 /* set when we want DEBUGCTLMSR_BTF */
> -#define TIF_ADDR32 27 /* 32-bit address space on 64 bits */
> +#define TIF_BLOCKSTEP 25 /* set when we want DEBUGCTLMSR_BTF */
> +#define TIF_ADDR32 26 /* 32-bit address space on 64 bits */
>
> #define _TIF_SSBD BIT(TIF_SSBD)
> #define _TIF_SPEC_IB BIT(TIF_SPEC_IB)
> @@ -112,7 +111,6 @@ struct thread_info {
> #define _TIF_SPEC_FORCE_UPDATE BIT(TIF_SPEC_FORCE_UPDATE)
> #define _TIF_FORCED_TF BIT(TIF_FORCED_TF)
> #define _TIF_BLOCKSTEP BIT(TIF_BLOCKSTEP)
> -#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
> #define _TIF_ADDR32 BIT(TIF_ADDR32)
>
> /* flags to check in __switch_to() */
> diff --git a/include/asm-generic/thread_info_tif.h b/include/asm-generic/thread_info_tif.h
> index da1610a78f92..b277fe06aee3 100644
> --- a/include/asm-generic/thread_info_tif.h
> +++ b/include/asm-generic/thread_info_tif.h
> @@ -48,4 +48,9 @@
> #define TIF_RSEQ 11 // Run RSEQ fast path
> #define _TIF_RSEQ BIT(TIF_RSEQ)
>
> +#ifdef HAVE_TIF_SINGLESTEP
> +#define TIF_SINGLESTEP 12 /* reenable singlestep on user return*/
> +#define _TIF_SINGLESTEP BIT(TIF_SINGLESTEP)
> +#endif
> +
> #endif /* _ASM_GENERIC_THREAD_INFO_TIF_H_ */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags
2026-03-20 10:42 [PATCH v14 0/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 1/4] s390: Rename TIF_SINGLE_STEP to TIF_SINGLESTEP Jinjie Ruan
2026-03-20 10:42 ` [PATCH v14 2/4] asm-generic: Move TIF_SINGLESTEP to generic TIF bits Jinjie Ruan
@ 2026-03-20 10:42 ` Jinjie Ruan
2026-04-01 10:55 ` Catalin Marinas
2026-03-20 10:42 ` [PATCH v14 4/4] selftests: sud_test: Support aarch64 Jinjie Ruan
3 siblings, 1 reply; 9+ messages in thread
From: Jinjie Ruan @ 2026-03-20 10:42 UTC (permalink / raw)
To: catalin.marinas, will, chenhuacai, kernel, hca, gor, agordeev,
borntraeger, svens, oleg, tglx, mingo, bp, dave.hansen, hpa, arnd,
shuah, kevin.brodsky, ruanjinjie, yeoreum.yun, anshuman.khandual,
thuth, ryan.roberts, mark.rutland, song, ziyao, linusw,
schuster.simon, jremus, akpm, mathieu.desnoyers, kmal, dvyukov,
reddybalavignesh9979, x86, linux-arm-kernel, linux-kernel,
loongarch, linux-s390, linux-arch, linux-kselftest
Use the generic TIF bits defined in <asm-generic/thread_info_tif.h> for
standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME,
TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining
them locally.
Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE,
TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts.
This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS
combined with the generic entry infrastructure (already used by arm64).
By the way, remove TIF_FREEZE because this flag became unused since
commit d88e4cb67197 ("freezer: remove now unused TIF_FREEZE").
Cc: Thomas Gleixner <tglx@kernel.org>
Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
arch/arm64/Kconfig | 1 +
arch/arm64/include/asm/thread_info.h | 61 ++++++++++++----------------
2 files changed, 27 insertions(+), 35 deletions(-)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 96fef01598be..33cf901fb1a0 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -224,6 +224,7 @@ config ARM64
select HAVE_SAMPLE_FTRACE_DIRECT_MULTI
select HAVE_BUILDTIME_MCOUNT_SORT
select HAVE_EFFICIENT_UNALIGNED_ACCESS
+ select HAVE_GENERIC_TIF_BITS
select HAVE_GUP_FAST
select HAVE_FTRACE_GRAPH_FUNC
select HAVE_FUNCTION_TRACER
diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h
index f89a15dc6ad5..57c37b05b961 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -58,42 +58,33 @@ void arch_setup_new_exec(void);
#endif
-#define TIF_SIGPENDING 0 /* signal pending */
-#define TIF_NEED_RESCHED 1 /* rescheduling necessary */
-#define TIF_NEED_RESCHED_LAZY 2 /* Lazy rescheduling needed */
-#define TIF_NOTIFY_RESUME 3 /* callback before returning to user */
-#define TIF_FOREIGN_FPSTATE 4 /* CPU's FP state is not current's */
-#define TIF_UPROBE 5 /* uprobe breakpoint or singlestep */
-#define TIF_MTE_ASYNC_FAULT 6 /* MTE Asynchronous Tag Check Fault */
-#define TIF_NOTIFY_SIGNAL 7 /* signal notifications exist */
-#define TIF_PATCH_PENDING 13 /* pending live patching update */
-#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
-#define TIF_FREEZE 19
-#define TIF_RESTORE_SIGMASK 20
-#define TIF_SINGLESTEP 21
-#define TIF_32BIT 22 /* 32bit process */
-#define TIF_SVE 23 /* Scalable Vector Extension in use */
-#define TIF_SVE_VL_INHERIT 24 /* Inherit SVE vl_onexec across exec */
-#define TIF_SSBD 25 /* Wants SSB mitigation */
-#define TIF_TAGGED_ADDR 26 /* Allow tagged user addresses */
-#define TIF_SME 27 /* SME in use */
-#define TIF_SME_VL_INHERIT 28 /* Inherit SME vl_onexec across exec */
-#define TIF_KERNEL_FPSTATE 29 /* Task is in a kernel mode FPSIMD section */
-#define TIF_TSC_SIGSEGV 30 /* SIGSEGV on counter-timer access */
-#define TIF_LAZY_MMU_PENDING 31 /* Ops pending for lazy mmu mode exit */
+/*
+ * Tell the generic TIF infrastructure which bits arm64 supports
+ */
+#define HAVE_TIF_NEED_RESCHED_LAZY
+#define HAVE_TIF_RESTORE_SIGMASK
+#define HAVE_TIF_SINGLESTEP
+
+#include <asm-generic/thread_info_tif.h>
+
+#define TIF_FOREIGN_FPSTATE 16 /* CPU's FP state is not current's */
+#define TIF_MTE_ASYNC_FAULT 17 /* MTE Asynchronous Tag Check Fault */
+#define TIF_32BIT 18 /* 32bit process */
+#define TIF_SVE 19 /* Scalable Vector Extension in use */
+#define TIF_SVE_VL_INHERIT 20 /* Inherit SVE vl_onexec across exec */
+#define TIF_SSBD 21 /* Wants SSB mitigation */
+#define TIF_TAGGED_ADDR 22 /* Allow tagged user addresses */
+#define TIF_SME 23 /* SME in use */
+#define TIF_SME_VL_INHERIT 24 /* Inherit SME vl_onexec across exec */
+#define TIF_KERNEL_FPSTATE 25 /* Task is in a kernel mode FPSIMD section */
+#define TIF_TSC_SIGSEGV 26 /* SIGSEGV on counter-timer access */
+#define TIF_LAZY_MMU_PENDING 27 /* Ops pending for lazy mmu mode exit */
-#define _TIF_SIGPENDING (1 << TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED)
-#define _TIF_NEED_RESCHED_LAZY (1 << TIF_NEED_RESCHED_LAZY)
-#define _TIF_NOTIFY_RESUME (1 << TIF_NOTIFY_RESUME)
-#define _TIF_FOREIGN_FPSTATE (1 << TIF_FOREIGN_FPSTATE)
-#define _TIF_PATCH_PENDING (1 << TIF_PATCH_PENDING)
-#define _TIF_UPROBE (1 << TIF_UPROBE)
-#define _TIF_32BIT (1 << TIF_32BIT)
-#define _TIF_SVE (1 << TIF_SVE)
-#define _TIF_MTE_ASYNC_FAULT (1 << TIF_MTE_ASYNC_FAULT)
-#define _TIF_NOTIFY_SIGNAL (1 << TIF_NOTIFY_SIGNAL)
-#define _TIF_TSC_SIGSEGV (1 << TIF_TSC_SIGSEGV)
+#define _TIF_FOREIGN_FPSTATE BIT(TIF_FOREIGN_FPSTATE)
+#define _TIF_32BIT BIT(TIF_32BIT)
+#define _TIF_SVE BIT(TIF_SVE)
+#define _TIF_MTE_ASYNC_FAULT BIT(TIF_MTE_ASYNC_FAULT)
+#define _TIF_TSC_SIGSEGV BIT(TIF_TSC_SIGSEGV)
#ifdef CONFIG_SHADOW_CALL_STACK
#define INIT_SCS \
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags
2026-03-20 10:42 ` [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
@ 2026-04-01 10:55 ` Catalin Marinas
2026-04-02 1:41 ` Jinjie Ruan
0 siblings, 1 reply; 9+ messages in thread
From: Catalin Marinas @ 2026-04-01 10:55 UTC (permalink / raw)
To: Jinjie Ruan
Cc: will, chenhuacai, kernel, hca, gor, agordeev, borntraeger, svens,
oleg, tglx, mingo, bp, dave.hansen, hpa, arnd, shuah,
kevin.brodsky, yeoreum.yun, anshuman.khandual, thuth,
ryan.roberts, mark.rutland, song, ziyao, linusw, schuster.simon,
jremus, akpm, mathieu.desnoyers, kmal, dvyukov,
reddybalavignesh9979, x86, linux-arm-kernel, linux-kernel,
loongarch, linux-s390, linux-arch, linux-kselftest
On Fri, Mar 20, 2026 at 06:42:21PM +0800, Jinjie Ruan wrote:
> Use the generic TIF bits defined in <asm-generic/thread_info_tif.h> for
> standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME,
> TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining
> them locally.
>
> Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE,
> TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts.
>
> This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS
> combined with the generic entry infrastructure (already used by arm64).
>
> By the way, remove TIF_FREEZE because this flag became unused since
> commit d88e4cb67197 ("freezer: remove now unused TIF_FREEZE").
>
> Cc: Thomas Gleixner <tglx@kernel.org>
> Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
> Reviewed-by: Linus Walleij <linusw@kernel.org>
> Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Given that it's touching multiple trees, I guess it's a series for
Andrew?
--
Catalin
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags
2026-04-01 10:55 ` Catalin Marinas
@ 2026-04-02 1:41 ` Jinjie Ruan
0 siblings, 0 replies; 9+ messages in thread
From: Jinjie Ruan @ 2026-04-02 1:41 UTC (permalink / raw)
To: Catalin Marinas
Cc: will, chenhuacai, kernel, hca, gor, agordeev, borntraeger, svens,
oleg, tglx, mingo, bp, dave.hansen, hpa, arnd, shuah,
kevin.brodsky, yeoreum.yun, anshuman.khandual, thuth,
ryan.roberts, mark.rutland, song, ziyao, linusw, schuster.simon,
jremus, akpm, mathieu.desnoyers, kmal, dvyukov,
reddybalavignesh9979, x86, linux-arm-kernel, linux-kernel,
loongarch, linux-s390, linux-arch, linux-kselftest
On 2026/4/1 18:55, Catalin Marinas wrote:
> On Fri, Mar 20, 2026 at 06:42:21PM +0800, Jinjie Ruan wrote:
>> Use the generic TIF bits defined in <asm-generic/thread_info_tif.h> for
>> standard thread flags (TIF_SIGPENDING, TIF_NEED_RESCHED, TIF_NOTIFY_RESUME,
>> TIF_RESTORE_SIGMASK, TIF_SINGLESTEP, etc.) instead of defining
>> them locally.
>>
>> Arm64-specific bits (TIF_FOREIGN_FPSTATE, TIF_MTE_ASYNC_FAULT, TIF_SVE,
>> TIF_SSBD, etc.) are renumbered to start at bit 16 to avoid conflicts.
>>
>> This enables RSEQ optimizations which require CONFIG_HAVE_GENERIC_TIF_BITS
>> combined with the generic entry infrastructure (already used by arm64).
>>
>> By the way, remove TIF_FREEZE because this flag became unused since
>> commit d88e4cb67197 ("freezer: remove now unused TIF_FREEZE").
>>
>> Cc: Thomas Gleixner <tglx@kernel.org>
>> Reviewed-by: Kevin Brodsky <kevin.brodsky@arm.com>
>> Reviewed-by: Linus Walleij <linusw@kernel.org>
>> Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
>> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
>
> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
>
> Given that it's touching multiple trees, I guess it's a series for
> Andrew?
Yes, this series touches x86, arm64, s390 and loongarch. It's best for
Andrew to help merge this in the -mm tree.
Moreover, the latter two arm64-related patches depend on patch serise
"arm64:
entry: Convert to Generic Entry" v14 being merged first, while the first
two patches can be merged in advance.
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v14 4/4] selftests: sud_test: Support aarch64
2026-03-20 10:42 [PATCH v14 0/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
` (2 preceding siblings ...)
2026-03-20 10:42 ` [PATCH v14 3/4] arm64: Use generic TIF bits for common thread flags Jinjie Ruan
@ 2026-03-20 10:42 ` Jinjie Ruan
2026-03-20 13:40 ` Linus Walleij
3 siblings, 1 reply; 9+ messages in thread
From: Jinjie Ruan @ 2026-03-20 10:42 UTC (permalink / raw)
To: catalin.marinas, will, chenhuacai, kernel, hca, gor, agordeev,
borntraeger, svens, oleg, tglx, mingo, bp, dave.hansen, hpa, arnd,
shuah, kevin.brodsky, ruanjinjie, yeoreum.yun, anshuman.khandual,
thuth, ryan.roberts, mark.rutland, song, ziyao, linusw,
schuster.simon, jremus, akpm, mathieu.desnoyers, kmal, dvyukov,
reddybalavignesh9979, x86, linux-arm-kernel, linux-kernel,
loongarch, linux-s390, linux-arch, linux-kselftest
From: kemal <kmal@cock.li>
Support aarch64 to test "Syscall User Dispatch" feature with
sud_test selftest testcase.
On qemu-kvm machine, the sud_benchmark test results are as below:
# ./sud_benchmark
Calibrating test set to last ~5 seconds...
test iterations = 24500000
Avg syscall time 208ns.
Enabling syscall trapping.
Caught sys_1c2
trapped_call_count 1, native_call_count 0.
Avg syscall time 213ns.
Interception overhead: 2.5% (+5ns).
Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
Signed-off-by: kemal <kmal@cock.li>
Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
---
tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c | 2 +-
tools/testing/selftests/syscall_user_dispatch/sud_test.c | 4 ++++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c b/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c
index 073a03702ff5..6059abe75cb3 100644
--- a/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c
+++ b/tools/testing/selftests/syscall_user_dispatch/sud_benchmark.c
@@ -41,7 +41,7 @@
* out of the box, but don't enable them until they support syscall user
* dispatch.
*/
-#if defined(__x86_64__) || defined(__i386__)
+#if defined(__x86_64__) || defined(__i386__) || defined(__aarch64__)
#define TEST_BLOCKED_RETURN
#endif
diff --git a/tools/testing/selftests/syscall_user_dispatch/sud_test.c b/tools/testing/selftests/syscall_user_dispatch/sud_test.c
index b855c6000287..3ffea2f4a66d 100644
--- a/tools/testing/selftests/syscall_user_dispatch/sud_test.c
+++ b/tools/testing/selftests/syscall_user_dispatch/sud_test.c
@@ -192,6 +192,10 @@ static void handle_sigsys(int sig, siginfo_t *info, void *ucontext)
((ucontext_t *)ucontext)->uc_mcontext.__gregs[REG_A0] =
((ucontext_t *)ucontext)->uc_mcontext.__gregs[REG_A7];
#endif
+#ifdef __aarch64__
+ ((ucontext_t *)ucontext)->uc_mcontext.regs[0] = (unsigned int)
+ ((ucontext_t *)ucontext)->uc_mcontext.regs[8];
+#endif
}
int setup_sigsys_handler(void)
--
2.34.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH v14 4/4] selftests: sud_test: Support aarch64
2026-03-20 10:42 ` [PATCH v14 4/4] selftests: sud_test: Support aarch64 Jinjie Ruan
@ 2026-03-20 13:40 ` Linus Walleij
0 siblings, 0 replies; 9+ messages in thread
From: Linus Walleij @ 2026-03-20 13:40 UTC (permalink / raw)
To: Jinjie Ruan
Cc: catalin.marinas, will, chenhuacai, kernel, hca, gor, agordeev,
borntraeger, svens, oleg, tglx, mingo, bp, dave.hansen, hpa, arnd,
shuah, kevin.brodsky, yeoreum.yun, anshuman.khandual, thuth,
ryan.roberts, mark.rutland, song, ziyao, schuster.simon, jremus,
akpm, mathieu.desnoyers, kmal, dvyukov, reddybalavignesh9979, x86,
linux-arm-kernel, linux-kernel, loongarch, linux-s390, linux-arch,
linux-kselftest
On Fri, Mar 20, 2026 at 11:41 AM Jinjie Ruan <ruanjinjie@huawei.com> wrote:
> From: kemal <kmal@cock.li>
>
> Support aarch64 to test "Syscall User Dispatch" feature with
> sud_test selftest testcase.
>
> On qemu-kvm machine, the sud_benchmark test results are as below:
>
> # ./sud_benchmark
> Calibrating test set to last ~5 seconds...
> test iterations = 24500000
> Avg syscall time 208ns.
> Enabling syscall trapping.
> Caught sys_1c2
> trapped_call_count 1, native_call_count 0.
> Avg syscall time 213ns.
> Interception overhead: 2.5% (+5ns).
>
> Reviewed-by: Yeoreum Yun <yeoreum.yun@arm.com>
> Signed-off-by: kemal <kmal@cock.li>
> Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com>
Reviewed-by: Linus Walleij <linusw@kernel.org>
Yours,
Linus Walleij
^ permalink raw reply [flat|nested] 9+ messages in thread