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Sun, 30 Aug 2026 16:18:37 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , Subject: [PATCH v10 07/13] iommu/arm-smmu-v3-kexec: Add a CD table parse helper Date: Sun, 30 Aug 2026 16:18:08 -0700 Message-ID: X-Mailer: git-send-email 2.43.0 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS3PEPF0000C37E:EE_|DM4PR12MB5964:EE_ X-MS-Office365-Filtering-Correlation-Id: 0561a06e-85f1-480d-e1a3-08df06ed0b1c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|376014|82310400026|7416014|1800799024|10067099003|11063799006|6133799003|5023799004|56012099006|18002099003|22082099003|3023799007; X-Microsoft-Antispam-Message-Info: 9s0B+BJ1P4V3UhI3NkSw6qGur3/Nu0dzVF0/6ABr99IZ/4MmB5Gh0WRSvauiqH92wMz/TD1I7JIeQF8HO6Zr2lLb1CFQL/TmcA1qpdEfU1LbG3daOuZGHtLfXGVvE+irmgbDmMBwHCoN3T/mtXwIXzvIlGXY8be1osPIhzMbviK5yJYVIVNIb0+LdttNhIoehSP+7almwlYb4SAzKSAiJre23iLdy3IuXV4qysw6dXPotrEyRND1eRIoXywLKMvLzQoPVgMKWl46giqG3VjYnXolyVB8Ll8lHKVtewIk8M9nTdNR1+/LybRbV20CjekXLTMWzAwRz7N/1V6ywUBowANP4uF8VZd+ZImAml7v4Di9eBL88oHP2cRO7bGGNu//xg84vxy3txLNEF5KnxxMGNkxeEX46FLUkjPJBI2TAdhKSs6c4sjwk+pZWfv0D/ltS8y3bBi/VjfurN9hTYgd3tKRywdBhwklqL3aR2pU/rsKT//mVZd8iLN9xveOsaPHY7jhShxFVM818HmicjNoP1QRcGwowK93GcQuYA+Rhttubt1hFJUTNklIjnCCVQHfOG0bqZ7nUHJnHigjyPboWJyCiUvMw77YO6jih0oRkc4QReyhIozpPoIRsF1yyO1QmtRuhi+HxJ4wKsokBGPG8QeC9V9/PDuScz00gRipDMq8D555V/ejA7sY931dE2ee3GU7nNYBTOY2a3moBAXn3A== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(376014)(82310400026)(7416014)(1800799024)(10067099003)(11063799006)(6133799003)(5023799004)(56012099006)(18002099003)(22082099003)(3023799007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: RzszFFD8DipqtSdGIuAGcG+bCcO3BGuPUZkccs6mTHbjGBaMo6nayYvuik0RENgLd1qsOAMATqyHmDlcgo0/NkG4PQ2r8fNbWsovlTv8XLE+1uy5zUVVdQFLjTXzOr5wNjjQpIvuqMvCVm8lpxNgS5WNX6LQCf+2sbFDd504QlkljEzSowXEJ1WJykfw5K/5W7aiksJyxyeJrkt7+uLDXVqOeHRpE9pfbU6I8O37or7fk0X/kp5GseFia12GbHcQv2mNkMZKGIsp8HqhlqH+nweoRg7z/IeU65kU9j8Q6FEvZrZGTGMHnVCF3EQeeGJHJrZbsSke8lZs9lXhaukLFNeRJ6yGbuu81kt4Ng+ckfTxhmfokcbs8qGMuStXV6A2sGwEsPjEf+yxPPG7mLx6wR7bI3uNsuNyS83d5xnE+cwhG146++1qTx7kX8T63wz2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Aug 2026 23:18:47.2399 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0561a06e-85f1-480d-e1a3-08df06ed0b1c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS3PEPF0000C37E.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5964 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260830_161856_128638_562DE930 X-CRM114-Status: GOOD ( 18.73 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org An S1 STE points to a CD table that both of the kexec flavors decode: the kdump adoption scans the CD table to reserve all the in-use ASIDs, and the live-update restoration claims the CD table via the KHO restore API. Add another read-only helper to the arm-smmu-v3-kexec.c: - arm_smmu_kexec_check_ste_cdtab() It validates the CD table geometry in an S1 STE against this kernel's own ssid_bits and the 2-level HW capability. And it accepts a linear CD table on the 2-level capable HW too, since a previous kernel might have used one, like the linear stream table. The CD table base gets validated against the table size as well, since the spec aligns a CD table to its own size, where an unaligned base would be a CONSTRAINED UNPREDICTABLE case: HW may zero its low bits or may fetch any CD in the table, so a scan reading such a base could miss the CDs in use. Reviewed-by: Jason Gunthorpe Assisted-by: Claude:claude-fable-5 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 3 + .../iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c | 57 +++++++++++++++++++ 2 files changed, 60 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h index 41d7a907b9ba2..1bcf6cb2ebb3c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h @@ -1261,6 +1261,9 @@ int arm_smmu_kexec_parse_strtab_linear(struct arm_smmu_device *smmu, int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, u64 l1_desc, u32 idx, phys_addr_t *l2_base); +int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, + phys_addr_t *cdtab, u32 *s1fmt, + u32 *max_contexts); #endif /* CONFIG_ARM_SMMU_V3_KEXEC */ #ifdef CONFIG_CRASH_DUMP diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c index b15e23df11b6d..700f63c7972e9 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-kexec.c @@ -164,3 +164,60 @@ int arm_smmu_kexec_check_strtab_l1_desc(struct arm_smmu_device *smmu, *l2_base = base; return 0; } + +/** + * arm_smmu_kexec_check_ste_cdtab() - Decode the CD table geometry of an STE + * @smmu: SMMU device of this kernel + * @ste0: first 64 bits of the previous kernel's S1 STE + * @cdtab: pointer to return the CD table's physical address + * @s1fmt: pointer to return the CD table format + * @max_contexts: pointer to return the number of CDs + * + * Note that a linear CD table on the 2-level capable hardware is accepted, as a + * previous kernel might have used one, like the linear stream table. + * + * Note that the spec requires a CD table to be aligned to its own size, so an + * unaligned @cdtab gets rejected here: HW may then zero the low bits or fetch + * any CD in the table, leaving the live ASIDs unknowable to this scan. + * + * Return: 0 on success with the three outputs set, or -EINVAL on a bad geometry + */ +int arm_smmu_kexec_check_ste_cdtab(struct arm_smmu_device *smmu, u64 ste0, + phys_addr_t *cdtab, u32 *s1fmt, + u32 *max_contexts) +{ + phys_addr_t base = ste0 & STRTAB_STE_0_S1CTXPTR_MASK; + u32 s1cdmax = FIELD_GET(STRTAB_STE_0_S1CDMAX, ste0); + u32 fmt = FIELD_GET(STRTAB_STE_0_S1FMT, ste0); + size_t size; + + if (!base || s1cdmax > smmu->ssid_bits) + return -EINVAL; + + if (fmt != STRTAB_STE_0_S1FMT_LINEAR && + fmt != STRTAB_STE_0_S1FMT_64K_L2) + return -EINVAL; + + /* Both kernels run on the same HW, so a genuine STE never has this */ + if (fmt == STRTAB_STE_0_S1FMT_64K_L2 && + !(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) + return -EINVAL; + + if (fmt == STRTAB_STE_0_S1FMT_LINEAR) + size = (1UL << s1cdmax) * sizeof(struct arm_smmu_cd); + else + size = DIV_ROUND_UP(1UL << s1cdmax, CTXDESC_L2_ENTRIES) * + sizeof(struct arm_smmu_cdtab_l1); + + /* + * An unaligned base is CONSTRAINED UNPREDICTABLE: HW may zero the low + * bits or fetch any CD in the table, so live ASIDs become unknowable. + */ + if (!IS_ALIGNED(base, size)) + return -EINVAL; + + *cdtab = base; + *s1fmt = fmt; + *max_contexts = 1U << s1cdmax; + return 0; +} -- 2.43.0