Re: [PATCH v4 03/10] iommu/arm-smmu-v3: Store IOTLB cache tags in struct arm_smmu_attach_state

[Nicolin Chen <nicolinc@nvidia.com>]

On Fri, Apr 10, 2026 at 05:47:09PM -0300, Jason Gunthorpe wrote:
> On Fri, Apr 10, 2026 at 11:52:01AM -0700, Nicolin Chen wrote:
> > > Only readers *with the possibility of concurrent access* should be
> > > marked with READ_ONCE. IIRC this is just the invalidation walker.
> > 
> > I added a cleanup patch to the beginning of the series and corrected
> > all the new reads/writes too.
> > 
> > > Places like this have to be protected by a lock or the whole thing is
> > > wrong, so it should have a lockdep annoation.
> > 
> > Hmm, is the lockdep_is_held() in rcu_dereference_protected() enough?
> 
> Yes.. but I didn't notice it there, not where I usually look for
> lockdeps :)

I added two new asserts in the find/get() and put notes in kdocs.

> But also that should have failed in your testing in the SVA case, so
> make sure you test with lockdep on, and segfault some app using SVA to
> trigger the error clean up flow.

Ack. I recall I tried SVA case with CONFIG_LOCKDEP=y. But it did
not cover the error clean up flow..

Reworking the SVA code, I found arm_smmu_update_s1_domain_cd_entry
is marked as __maybe_unused and not getting called anywhere(?). Do
you recall why we kept it?

> > > But why does arm_smmu_mm_release() need a tag in the first place? ASID
> > > isn't going to be used when EPD0|EPD1 is set, so the tag can just be
> > > 0. Probably make a patch with that change early on..
> > 
> > I see. I added a cleanup patch.
> 
> Also double check it still generates a hitless update, I think it
> should but worth confirming.

Both EDP0 and ASID are in the word0 of a CD:
    CTXDESC_CD_0_ASID
    CTXDESC_CD_0_TCR_EPD0

So, used_qword_diff is 0x1. I think we are good.

> Also is ASID 0 used at all?

Setting EPD0/1 disables any PT walk. HW could still use an ASID to
match the cache lines. But, in this release pathway, the cache will
be flushed also. And completely aborting any ASID usage makes sense
to me. So, passing ASID=0 to guarantee a TLB miss should work.

Thanks
Nicolin