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Thu, 12 Nov 2026 08:48:08 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface X-Archived-By: MIME-Version: 1.0 X-ThreadId: An903QizF2Ds Date: Thu, 12 Nov 2026 14:47:28 +0100 From: "Arnd Bergmann" To: "Arnd Bergmann" , linux-mm@kvack.org Cc: "Andrew Morton" , "Andreas Larsson" , "Christophe Leroy" , "Dave Hansen" , "David Hildenbrand (Red Hat)" , "Jason Gunthorpe" , "Linus Walleij" , "Lorenzo Stoakes" , "Matthew Wilcox" , "Malin Jonsson" , "Richard Weinberger" , "Russell King" , linux-arm-kernel@lists.infradead.org, linux-fsdevel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, x86@kernel.org Message-Id: In-Reply-To: <20261112112528.1116405-2-arnd@kernel.org> References: <20261112112528.1116405-1-arnd@kernel.org> <20261112112528.1116405-2-arnd@kernel.org> Subject: Re: [PATCH v2 1/6] ARM: remove support for highmem on VIVT Content-Type: text/plain Content-Transfer-Encoding: 7bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20261112_054827_003154_B5FCC947 X-CRM114-Status: UNSURE ( 9.77 ) X-CRM114-Notice: Please train this message. X-Spam-Score: -2.1 (--) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" X-Spam-Status: No, score=-10.9 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Nov 12, 2026, at 12:25, Arnd Bergmann wrote: > --- a/arch/arm/mach-omap2/Kconfig > +++ b/arch/arm/mach-omap2/Kconfig > @@ -135,7 +135,7 @@ config ARCH_OMAP2PLUS_TYPICAL > bool "Typical OMAP configuration" > default y > select AEABI > - select HIGHMEM > + select HIGHMEM if !CPU_CACHE_VIVT > select I2C > select I2C_OMAP > select MENELAUS if ARCH_OMAP2 I'm not sure where this comes from, it was probably a mistake during rebasing. None of the V6/V7 CPUs can be built with CPU_CACHE_VIVT, so I've dropped this part. Arnd