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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b72bfa0f37csm1559184066b.64.2025.11.12.02.37.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Nov 2025 02:37:31 -0800 (PST) Message-ID: Date: Wed, 12 Nov 2025 11:37:27 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 16/21] drm/msm/adreno: Do CX GBIF config before GMU start To: Akhil P Oommen , Rob Clark , Bjorn Andersson , Konrad Dybcio , Sean Paul , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek , Jordan Crouse , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Connor Abbott Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org References: <20251110-kaana-gpu-support-v2-0-bef18acd5e94@oss.qualcomm.com> <20251110-kaana-gpu-support-v2-16-bef18acd5e94@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20251110-kaana-gpu-support-v2-16-bef18acd5e94@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: sT_48yXcY-Y4jat_Q-bgweOsoGglZcM5 X-Proofpoint-ORIG-GUID: sT_48yXcY-Y4jat_Q-bgweOsoGglZcM5 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEyMDA4NSBTYWx0ZWRfXzwAYa87A5Mp0 Obsl0kI/UVlIQgQi5Y36kC/qv6IomxL8mQz9ZTHEB8YeNxt/KLOLMnDpEqKxgP9W5KJYAfmzjRv JstDOdmRk34elWc+GKzwzdWv7lJ0nk8q6EhHtlIrimPxy4lwde0a1OenNTf7SMRq4brG1D9x28L SxB27DrBCduwVYp8Lk83escV6uLEc6ULRnJMc+3XHZSv702Kd8+EBbqCiBCO0B0uXl7YbpiQJaC 1XiwO4QGkVL2FMsi6/Ez+fP5qPCqSbKj8kXl/DAzdidAx2ViENTTA2UZA1JxdbI5h5NdxaV3KVs pxlc53xmrctjqsAMgRtkQDRD2rcLsSxlm3ED7UuX7+STpcIy/XvKuKnbw8DbR67wg+myjNMd2OK 7xHVzsbJ6fk098cjyPHJGbwJomKAYQ== X-Authority-Analysis: v=2.4 cv=L/0QguT8 c=1 sm=1 tr=0 ts=6914636d cx=c_pps a=hnmNkyzTK/kJ09Xio7VxxA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=XltbfQAJAwjtl7jyp1EA:9 a=QEXdDO2ut3YA:10 a=PEH46H7Ffwr30OY-TuGO:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-12_03,2025-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 spamscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511120085 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20251112_023734_070282_F05A8C24 X-CRM114-Status: GOOD ( 24.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 11/10/25 5:37 PM, Akhil P Oommen wrote: > GMU lies on the CX domain and accesses CX GBIF. So do CX GBIF > configurations before GMU wakes up. This was not a problem so far, but > A840 GPU is very sensitive to this requirement. Also, move these > registers to the catalog. > > Signed-off-by: Akhil P Oommen > --- [...] > + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ > + for (int i = 0; (gbif_cx && gbif_cx[i].offset); i++) > + gpu_write(gpu, gbif_cx[i].offset, gbif_cx[i].value); We haven't been doing this a lot in the GPU driver, but adding a .num_entries-like field is both more memory efficient and less error-prone > + > + /* For A7x and newer, do the CX GBIF configurations before GMU wake up */ duplicate comment > + if (adreno_is_a8xx(adreno_gpu)) { > + gpu_write(gpu, REG_A8XX_GBIF_CX_CONFIG, 0x20023000); > + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); Either set this prio value here, or in a8xx_gpu.c > + } > + > /* Set up the lowest idle level on the GMU */ > a6xx_gmu_power_config(gmu); > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > index 029f7bd25baf..66771958edb2 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c > @@ -1265,17 +1265,20 @@ static int hw_init(struct msm_gpu *gpu) > /* enable hardware clockgating */ > a6xx_set_hwcg(gpu, true); > > - /* VBIF/GBIF start*/ > - if (adreno_is_a610_family(adreno_gpu) || > - adreno_is_a640_family(adreno_gpu) || > - adreno_is_a650_family(adreno_gpu) || > - adreno_is_a7xx(adreno_gpu)) { > + /* For gmuwrapper implementations, do the VBIF/GBIF CX configuration here */ > + if (adreno_is_a610_family(adreno_gpu)) { > gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620); a640/650 family GPUs didn't receive a .gbif_cx addition in the catalog to match > gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620); > gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620); > gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620); > - gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, > - adreno_is_a7xx(adreno_gpu) ? 0x2120212 : 0x3); > + } > + > + if (adreno_is_a610_family(adreno_gpu) || > + adreno_is_a640_family(adreno_gpu) || > + adreno_is_a650_family(adreno_gpu)) { > + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3); > + } else if (adreno_is_a7xx(adreno_gpu)) { > + gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x2120212); > } else { > gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3); Downstream seems to set QOS_CNTL at the same time as QSB_SIDEn for these targets > } > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > index 031ca0e4b689..cf700f7de09b 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h > @@ -46,6 +46,7 @@ struct a6xx_info { > const struct adreno_protect *protect; > const struct adreno_reglist_list *pwrup_reglist; > const struct adreno_reglist_list *ifpc_reglist; > + const struct adreno_reglist *gbif_cx; > const struct adreno_reglist_pipe *nonctxt_reglist; > u32 gmu_chipid; > u32 gmu_cgc_mode; > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index 2ef69161f1d0..ad140b0d641d 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -500,6 +500,9 @@ static int hw_init(struct msm_gpu *gpu) > > gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0); > > + /* Increase priority of GMU traffic over GPU traffic */ > + gmu_write(gmu, REG_A6XX_GMU_MRC_GBIF_QOS_CTRL, 0x33); Kgsl (later) added this for A740 too - would it be beneficial to enable unconditionally on gen7+? Konrad