On Mon, Apr 20, 2026 at 07:08:01PM +0100, Mark Brown wrote:
> On Mon, Apr 20, 2026 at 02:13:34AM +0100, Daniel Golle wrote:
> 
> > +static int mt2701_afe_hdmi_trigger(struct snd_pcm_substream *substream, int cmd,
> > +				   struct snd_soc_dai *dai)
> > +{
> > +	struct mtk_base_afe *afe = snd_soc_dai_get_drvdata(dai);
> > +
> > +	switch (cmd) {
> > +	case SNDRV_PCM_TRIGGER_START:
> > +	case SNDRV_PCM_TRIGGER_RESUME:
> > +		/* Ungate HDMI and SPDIF power islands. */
> > +		regmap_update_bits(afe->regmap, AUDIO_TOP_CON0,
> > +				   AUDIO_TOP_CON0_PDN_HDMI_CK |
> > +				   AUDIO_TOP_CON0_PDN_SPDIF_CK, 0);
> 
> It looks like we have clock API clocks for HDMI and S/PDIF on this SoC
> (see clk-mt2701-aud.c) - are there going to be problem with peering
> directly at the register?  We do manage some clocks via the clock API
> but not those ones.

Yeah, you are right. That came from a super-old vendor driver and I
didn't realise the exact same gate bits are alrady driven by the
clock driver. I'll drop that and prepare v3...