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[34.83.236.195]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3614195a9f0sm20471832a91.9.2026.04.23.11.43.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Apr 2026 11:43:42 -0700 (PDT) Date: Thu, 23 Apr 2026 18:43:37 +0000 From: Samiullah Khawaja To: Will Deacon Cc: Jason Gunthorpe , Evangelos Petrongonas , Robin Murphy , Joerg Roedel , Nicolin Chen , Pranjal Shrivastava , Lu Baolu , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, nh-open-source@amazon.com, Zeev Zilberman , dmatlack@google.com, pasha.tatashin@soleen.com Subject: Re: [PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation Message-ID: References: <20260420123221.20801-1-epetron@amazon.de> <20260420124032.GO2577880@ziepe.ca> <20260422064431.GA49867@dev-dsk-epetron-1c-1d4d9719.eu-west-1.amazon.com> <20260422162351.GK3611611@ziepe.ca> <20260423142326.GP3611611@ziepe.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260423_114346_913575_DBE73380 X-CRM114-Status: GOOD ( 15.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Apr 23, 2026 at 06:07:23PM +0100, Will Deacon wrote: >On Thu, Apr 23, 2026 at 11:23:26AM -0300, Jason Gunthorpe wrote: >> On Thu, Apr 23, 2026 at 10:47:49AM +0100, Will Deacon wrote: >> > > Does iommu-pages provide a mechanism to map the memory as non-cacheable >> > > if the SMMU isn't coherent? >> >> No, it has to use CMOs today. >> >> It looks like all the stuff dma_alloc_coherent does to make a >> non-cached mapping are pretty arch specific. I don't know if there is >> a way we could make more general code get a struct page into an >> uncached KVA and meet all the arch rules? >> >> I also think dma_alloc_coherent is far to complex, with pools and >> more, to support KHO. Agreed. dma_alloc_* is too complex with pools, CMAs and what not to support fully in KHO. > >I wonder if there's scope for supporting just some subset of it? We have been experimenting with something like this. We have a usecase where memory needs to be preserved but we want to avoid invasive changes in the driver. If it's not a crazy idea, maybe we can start with a very limited scope of providing preservation for a subset of allocations done through the DMA API? I can send out my proof of concept as an RFC after I'm done with the next revision of my IOMMU persistence series. WDYT? Sami