On Sat, Feb 21, 2026 at 09:35:52PM +0300, Aleksandr Shubin wrote: > Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM > controllers with ones supported by pwm-sun4i driver. > > This patch adds a PWM controller driver for Allwinner's D1, > T113-S3 and R329 SoCs. The main difference between these SoCs > is the number of channels defined by the DT property. > > Co-developed-by: Brandon Cheo Fusi > Signed-off-by: Brandon Cheo Fusi > Signed-off-by: Aleksandr Shubin > --- > drivers/pwm/Kconfig | 10 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-sun8i.c | 393 ++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 404 insertions(+) > create mode 100644 drivers/pwm/pwm-sun8i.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 6f3147518376..44d844eba589 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -736,6 +736,16 @@ config PWM_SUN4I > To compile this driver as a module, choose M here: the module > will be called pwm-sun4i. > > +config PWM_SUN8I > + tristate "Allwinner D1/T113s/R329 PWM support" > + depends on ARCH_SUNXI || COMPILE_TEST > + depends on COMMON_CLK > + help > + Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs. > + > + To compile this driver as a module, choose M here: the module > + will be called pwm-sun8i. > + > config PWM_SUNPLUS > tristate "Sunplus PWM support" > depends on ARCH_SUNPLUS || COMPILE_TEST > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index 0dc0d2b69025..ba2e0ec7fc17 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -67,6 +67,7 @@ obj-$(CONFIG_PWM_STM32) += pwm-stm32.o > obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o > obj-$(CONFIG_PWM_STMPE) += pwm-stmpe.o > obj-$(CONFIG_PWM_SUN4I) += pwm-sun4i.o > +obj-$(CONFIG_PWM_SUN8I) += pwm-sun8i.o > obj-$(CONFIG_PWM_SUNPLUS) += pwm-sunplus.o > obj-$(CONFIG_PWM_TEGRA) += pwm-tegra.o > obj-$(CONFIG_PWM_TH1520) += pwm_th1520.o > diff --git a/drivers/pwm/pwm-sun8i.c b/drivers/pwm/pwm-sun8i.c > new file mode 100644 > index 000000000000..6e196f31314b > --- /dev/null > +++ b/drivers/pwm/pwm-sun8i.c > @@ -0,0 +1,393 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329) > + * > + * Limitations: > + * - When the parameters change, the current running period is not completed > + * and new settings are applied immediately. > + * - The PWM output goes to a HIGH-Z state when the channel is disabled. > + * - Changing the clock configuration (SUN8I_PWM_CLK_CFG) > + * may cause a brief output glitch. > + * > + * Copyright (c) 2023 Aleksandr Shubin > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define SUN8I_PWM_CLK_CFG(pair) (0x20 + ((pair) * 0x4)) A word about the range of `pair` would be good. Something like: /* * Shared clock register. SUN8I_PWM_CLK_CFG(pair) configures the settings * for channels 2·pair and 2·pair+1. Maximal value for pair is hardware * dependant, it cannot be bigger than 8. */ > +#define SUN8I_PWM_CLK_CFG_SRC GENMASK(8, 7) > +#define SUN8I_PWM_CLK_SRC_HOSC 0x0 > +#define SUN8I_PWM_CLK_SRC_BUS 0x1 SUN8I_PWM_CLK_SRC_HOSC and SUN8I_PWM_CLK_SRC_BUS are values for SUN8I_PWM_CLK_CFG_SRC, right? It would be great if they were named SUN8I_PWM_CLK_CFG_SRC_HOSC and SUN8I_PWM_CLK_CFG_SRC_BUS then. And then it might be sensible to define it to FIELD_PREP(SUN8I_PWM_CLK_CFG_SRC, 1) (and 0 respectively). I hope there is no conflict with the reference manual. Speaking of the reference manual: Is there a public one? If yes, adding a link to it would be awesome. > +#define SUN8I_PWM_CLK_CFG_DIV_M GENMASK(3, 0) > +#define SUN8I_PWM_CLK_DIV_M_MAX 8 > + > +#define SUN8I_PWM_CLK_GATE 0x40 > +#define SUN8I_PWM_CLK_GATE_BYPASS(chan) BIT((chan) + 16) > +#define SUN8I_PWM_CLK_GATE_GATING(chan) BIT(chan) > + > +#define SUN8I_PWM_ENABLE 0x80 > +#define SUN8I_PWM_ENABLE_EN(chan) BIT(chan) > + > +#define SUN8I_PWM_CTL(chan) (0x100 + (chan) * 0x20) > +#define SUN8I_PWM_CTL_ACT_STA BIT(8) > +#define SUN8I_PWM_CTL_PRESCAL_K GENMASK(7, 0) > +#define SUN8I_PWM_CTL_PRESCAL_K_MAX field_max(SUN8I_PWM_CTL_PRESCAL_K) > + > +#define SUN8I_PWM_PERIOD(chan) (0x104 + (chan) * 0x20) > +#define SUN8I_PWM_PERIOD_ENTIRE_CYCLE GENMASK(31, 16) > +#define SUN8I_PWM_PERIOD_ACT_CYCLE GENMASK(15, 0) > + > +#define SUN8I_PWM_PCNTR_SIZE BIT(16) This is unused (apart from the comment below). I'm unsure if this is a bit field, if so to which register? Does it need a comment? Or should it be dropped? From the discussion below, should this be field_max(SUN8I_PWM_PERIOD_ACT_CYCLE)? (The value is different then the calculations below needed some adaption if that is chosen.) > +/* > + * SUN8I_PWM_MAGIC is used to quickly compute the values of the clock dividers > + * div_m (SUN8I_PWM_CLK_CFG_DIV_M) & prescale_k (SUN8I_PWM_CTL_PRESCAL_K) > + * without using a loop. These dividers limit the # of cycles in a period > + * to SUN8I_PWM_PCNTR_SIZE (65536) by applying a scaling factor of > + * 1 / (div_m * (prescale_k + 1)) to the clock source. Here div_m is a plain divider, ... > + * > + * SUN8I_PWM_MAGIC is derived by solving for div_m and prescale_k > + * such that for a given requested period, > + * > + * i) div_m is minimized for any prescale_k ≤ SUN8I_PWM_CTL_PRESCAL_K_MAX, > + * ii) prescale_k is minimized. > + * > + * The derivation proceeds as follows, with val = # of cycles for requested > + * period: > + * > + * for a given value of div_m we want the smallest prescale_k such that > + * > + * (val >> div_m) // (prescale_k + 1) ≤ 65536 (= SUN8I_PWM_PCNTR_SIZE) ... and here it is a shift. I assume that above 1 << div_m is actually meant, right? > + * This is equivalent to: > + * > + * (val >> div_m) ≤ 65536 * (prescale_k + 1) + prescale_k > + * ⟺ (val >> div_m) ≤ 65537 * prescale_k + 65536 > + * ⟺ (val >> div_m) - 65536 ≤ 65537 * prescale_k > + * ⟺ ((val >> div_m) - 65536) / 65537 ≤ prescale_k > + * > + * As prescale_k is integer, this becomes > + * > + * ((val >> div_m) - 65536) // 65537 ≤ prescale_k > + * > + * And is minimized at > + * > + * ((val >> div_m) - 65536) // 65537 > + * > + * Now we pick the smallest div_m that satifies prescale_k ≤ 255 > + * (i.e SUN8I_PWM_CTL_PRESCAL_K_MAX), > + * > + * ((val >> div_m) - 65536) // 65537 ≤ 255 > + * ⟺ (val >> div_m) - 65536 ≤ 255 * 65537 + 65536 > + * ⟺ val >> div_m ≤ 255 * 65537 + 2 * 65536 > + * ⟺ val >> div_m < (255 * 65537 + 2 * 65536 + 1) > + * ⟺ div_m = fls((val) / (255 * 65537 + 2 * 65536 + 1)) > + * > + * Suggested by Uwe Kleine-König > + */ > +#define SUN8I_PWM_MAGIC (255 * 65537 + 2 * 65536 + 1) > +#define SUN8I_PWM_DIV_CONST 65537 > [...] > +static int sun8i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > +{ > + struct sun8i_pwm_chip *sun8i_chip = to_sun8i_pwm_chip(chip); > + u64 bus_rate, hosc_rate, val, ent_cycle, act_cycle; > + u32 clk_gate, clk_cfg, pwm_en, ctl, reg_period; > + u32 prescale_k, div_m; > + u64 clk_src_rate; > + u8 clk_src; > + > + pwm_en = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_ENABLE); > + clk_gate = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_CLK_GATE); > + > + if (!state->enabled) { > + if (state->enabled != pwm->state.enabled) { Can we make this if (pwm_en & SUN8I_PWM_ENABLE_EN(pwm->hwpwm)) { ? Then it depends on the hardware settings instead of cached state. Same for the other usage of pwm->state below. > + clk_gate &= ~SUN8I_PWM_CLK_GATE_GATING(pwm->hwpwm); > + pwm_en &= ~SUN8I_PWM_ENABLE_EN(pwm->hwpwm); > + sun8i_pwm_writel(sun8i_chip, pwm_en, SUN8I_PWM_ENABLE); > + sun8i_pwm_writel(sun8i_chip, clk_gate, SUN8I_PWM_CLK_GATE); > + } > + return 0; > + } > + > + ctl = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_CTL(pwm->hwpwm)); > + clk_cfg = sun8i_pwm_readl(sun8i_chip, SUN8I_PWM_CLK_CFG(pwm->hwpwm / 2)); > + hosc_rate = clk_get_rate(sun8i_chip->clk_hosc); > + bus_rate = clk_get_rate(sun8i_chip->clk_apb); > + > [...] > +static int sun8i_pwm_probe(struct platform_device *pdev) > +{ > + struct pwm_chip *chip; > + struct sun8i_pwm_chip *sun8i_chip; > + struct clk *clk_bus; > + struct reset_control *rst; > + u32 npwm; > + int ret; > + > + ret = of_property_read_u32(pdev->dev.of_node, "allwinner,npwms", &npwm); > + if (ret < 0) > + return dev_err_probe(&pdev->dev, ret, > + "Failed to get allwinner,npwms\n"); I failed to reply to your question about a non-vendored name for this in v10 (https://lore.kernel.org/linux-pwm/CAF4idNmDMQpFppUvCBbC1=SNMQBrTOqmFO60SMvKvaHvNJy=Bg@mail.gmail.com). "npwms" would be good. > + if (npwm < 1 || npwm > 16) > + return dev_err_probe(&pdev->dev, -EINVAL, > + "Invalid allwinner,npwms\n"); I think there is a corner case if npwm is odd. In that case the last channel must not check for hwpwm ^ 1 being enabled in .apply(). So either .apply() should be more clever, or only even values for npwm should be supported. > + chip = devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*sun8i_chip)); > + if (IS_ERR(chip)) > + return PTR_ERR(chip); > + sun8i_chip = to_sun8i_pwm_chip(chip); > + > + sun8i_chip->base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(sun8i_chip->base)) > + return PTR_ERR(sun8i_chip->base); > [...] Best regards Uwe