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[34.124.234.44]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3664db4f5fbsm2341255a91.15.2026.05.08.06.12.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 06:13:02 -0700 (PDT) Date: Fri, 8 May 2026 13:12:56 +0000 From: Pranjal Shrivastava To: Jason Gunthorpe Cc: Nicolin Chen , Will Deacon , Joerg Roedel , Jean-Philippe Brucker , Robin Murphy , Catalin Marinas , =?utf-8?Q?Miko=C5=82aj?= Lenczewski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits Message-ID: References: <20260503135413.1108138-1-nicolinc@nvidia.com> <20260508123550.GB9254@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260508123550.GB9254@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260508_061304_432476_7CB72F38 X-CRM114-Status: GOOD ( 19.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 08, 2026 at 09:35:50AM -0300, Jason Gunthorpe wrote: > On Thu, May 07, 2026 at 10:30:14PM +0000, Pranjal Shrivastava wrote: > > > @@ -92,6 +92,16 @@ void arm_smmu_make_sva_cd(struct arm_smmu_cd *target, > > > > > > target->data[1] = cpu_to_le64(virt_to_phys(mm->pgd) & > > > CTXDESC_CD_1_TTB0_MASK); > > > + > > > + /* > > > + * Enable Hardware Access and Dirty updates (DBM) if supported. > > > + * This is safe to enable by default, as PTE_WRITE and PTE_DBM > > > + * share the same bit. > > > + */ > > > + if (master->smmu->features & ARM_SMMU_FEAT_HA) > > > + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA); > > > + if (master->smmu->features & ARM_SMMU_FEAT_HD) > > > + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD); > > > > IIUC, we should be setting these if IO_PGTABLE_QUIRK_ARM_HD is present? > > SVA does not use IO_PGTABLE at all, and it directly constructs its own > CD. > > No relation between those two flows. I understand that but I mean we need to know if the system supports HTTU ? Like for SMMU we use the IO_PGTABLE_QUIRK, shouldn't we be checking if the CPU's tables support HTTU? Are we assuming that if the SMMU IDR presents HTTU capability the MMU would also have it? I think an unconditional enablement is risky as we may not have system-wide HTTU support. If we look at arm_smmu_master_sva_supported, the driver already maintains a strict agreement between the CPU and SMMU for SVA. It checks sanitized CPU ID registers for things like PARANGE & ASIDBITS, and it uses system_supports_bbml2_noabort() to decide whether to enable FEAT_BBML2. Shouldn't we follow this exact same pattern for HTTU ? We should probably be checking cpu_has_hw_af() (from asm/cpufeature.h) in the SVA support check or here if we wanna enable HTTU. Thanks, Praan