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[34.38.181.8]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-48e531578c8sm38692025e9.34.2026.05.07.02.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 02:24:03 -0700 (PDT) Date: Thu, 7 May 2026 09:23:58 +0000 From: Mostafa Saleh To: Jason Gunthorpe Cc: iommu@lists.linux.dev, Jonathan Hunter , Joerg Roedel , linux-arm-kernel@lists.infradead.org, linux-tegra@vger.kernel.org, Robin Murphy , Thierry Reding , Krishna Reddy , Will Deacon , David Matlack , Pasha Tatashin , patches@lists.linux.dev, Samiullah Khawaja Subject: Re: [PATCH 8/9] iommu/arm-smmu-v3: Directly encode CMDQ_OP_SYNC Message-ID: References: <0-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com> <8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <8-v1-b7dc0a0d4aa0+3723d-smmu_no_cmdq_ent_jgg@nvidia.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260507_022407_589836_67C4CB4B X-CRM114-Status: GOOD ( 24.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 01, 2026 at 11:29:17AM -0300, Jason Gunthorpe wrote: > Change the flow so the caller controls the CS field and remove the > weird u64p_replace_bits() thing to override it. > > Signed-off-by: Jason Gunthorpe Reviewed-by: Mostafa Saleh Thanks, Mostafa > --- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 42 ++++++++------------- > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 16 ++++++-- > 2 files changed, 27 insertions(+), 31 deletions(-) > > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > index 0cdf0752ff6d62..8147b9cdcc6b99 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c > @@ -308,16 +308,6 @@ static int arm_smmu_cmdq_build_cmd(struct arm_smmu_cmd *cmd_out, > case CMDQ_OP_TLBI_EL2_ASID: > cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); > break; > - case CMDQ_OP_CMD_SYNC: > - if (ent->sync.msiaddr) { > - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_IRQ); > - cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; > - } else { > - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); > - } > - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH); > - cmd[0] |= FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); > - break; > default: > return -ENOENT; > } > @@ -350,23 +340,24 @@ static void arm_smmu_cmdq_build_sync_cmd(struct arm_smmu_cmd *cmd, > struct arm_smmu_cmdq *cmdq, u32 prod) > { > struct arm_smmu_queue *q = &cmdq->q; > - struct arm_smmu_cmdq_ent ent = { > - .opcode = CMDQ_OP_CMD_SYNC, > - }; > + u64 msiaddr = 0; > + unsigned int cs; > > /* > * Beware that Hi16xx adds an extra 32 bits of goodness to its MSI > * payload, so the write will zero the entire command on that platform. > */ > - if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { > - ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * > - q->ent_dwords * 8; > + if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) { > + cs = CMDQ_SYNC_0_CS_NONE; > + } else if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { > + cs = CMDQ_SYNC_0_CS_IRQ; > + msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * > + q->ent_dwords * 8; > + } else { > + cs = CMDQ_SYNC_0_CS_SEV; > } > > - arm_smmu_cmdq_build_cmd(cmd, &ent); > - if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) > - u64p_replace_bits(&cmd->data[0], CMDQ_SYNC_0_CS_NONE, > - CMDQ_SYNC_0_CS); > + *cmd = arm_smmu_make_cmd_sync(cs, msiaddr); > } > > void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, > @@ -383,9 +374,6 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, > struct arm_smmu_cmd cmd; > u32 cons = readl_relaxed(q->cons_reg); > u32 idx = FIELD_GET(CMDQ_CONS_ERR, cons); > - struct arm_smmu_cmdq_ent cmd_sync = { > - .opcode = CMDQ_OP_CMD_SYNC, > - }; > > dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, > idx < ARRAY_SIZE(cerror_str) ? cerror_str[idx] : "Unknown"); > @@ -419,10 +407,10 @@ void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, > dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd.data[i]); > > /* Convert the erroneous command into a CMD_SYNC */ > - arm_smmu_cmdq_build_cmd(&cmd, &cmd_sync); > - if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) > - u64p_replace_bits(&cmd.data[0], CMDQ_SYNC_0_CS_NONE, > - CMDQ_SYNC_0_CS); > + cmd = arm_smmu_make_cmd_sync( > + arm_smmu_cmdq_needs_busy_polling(smmu, cmdq) ? > + CMDQ_SYNC_0_CS_NONE : CMDQ_SYNC_0_CS_SEV, > + 0); > > queue_write(Q_ENT(q, cons), cmd.data, q->ent_dwords); > } > diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > index 194f73cabef5c9..538380de7d48a0 100644 > --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h > @@ -571,6 +571,18 @@ static inline struct arm_smmu_cmd arm_smmu_make_cmd_atc_inv_all(u32 sid, > return arm_smmu_make_cmd_atc_inv(sid, ssid, 0, ATC_INV_SIZE_ALL); > } > > +static inline struct arm_smmu_cmd arm_smmu_make_cmd_sync(unsigned int cs, > + u64 msiaddr) > +{ > + struct arm_smmu_cmd cmd = arm_smmu_make_cmd_op(CMDQ_OP_CMD_SYNC); > + > + cmd.data[0] |= FIELD_PREP(CMDQ_SYNC_0_CS, cs) | > + FIELD_PREP(CMDQ_SYNC_0_MSH, ARM_SMMU_SH_ISH) | > + FIELD_PREP(CMDQ_SYNC_0_MSIATTR, ARM_SMMU_MEMATTR_OIWB); > + cmd.data[1] |= msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; > + return cmd; > +} > + > /* Event queue */ > #define EVTQ_ENT_SZ_SHIFT 5 > #define EVTQ_ENT_DWORDS ((1 << EVTQ_ENT_SZ_SHIFT) >> 3) > @@ -648,10 +660,6 @@ struct arm_smmu_cmdq_ent { > u8 tg; > u64 addr; > } tlbi; > - > - struct { > - u64 msiaddr; > - } sync; > }; > }; > > -- > 2.43.0 >