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Thu, 21 May 2026 14:07:36 -0700 Date: Thu, 21 May 2026 14:07:34 -0700 From: Nicolin Chen To: Bjorn Helgaas CC: , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v6 1/3] PCI: Add pci_ats_required() for CXL.cache capable devices Message-ID: References: <05044d2113e20d81f96677ba53605311662b6b10.1779392420.git.nicolinc@nvidia.com> <20260521205723.GA184317@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260521205723.GA184317@bhelgaas> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF0000009E:EE_|DM4PR12MB7671:EE_ X-MS-Office365-Filtering-Correlation-Id: 686685da-7467-4663-d957-08deb77d0af1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|376014|7416014|82310400026|11063799006|6133799003|18002099003|22082099003|56012099003|4143699003; X-Microsoft-Antispam-Message-Info: xOsD/y5SpGcYKV1NNka3piNktbA2nnZY9RYh58GIixK0EJYxHM0BXv2WtJxRR3vDEUHlLPKr5o/VzWLtaqLXYElc/6awarcJZQEHQUv+7MF/Wo06aO9qm10+NHNVp47D0yRlLtcOJj1wSJK8KWtTWvh97PDsvEVUZLh+u7KNReV3ugedQ1RodpxpKcgbnavzl6MqWz0bCfvPyQyCHEgzjOpV9xxtM9sEaPVb1JERiOm7Qu1litGntZnzPBJkt+WoT+PX7mbZfr4qJz8Go7pCPKrK3ak1xbTLK+19GUMXXcJGeO2k/7VVzEOvzuxi+92W+abDE3xtuII1cTCiJZ6kk42QmimiyGwCR5CEcSIOmpt9EAMYnP2fqHzHo0wNKglukubmE/yMFkt4fU6pyV4os4iWLwHeS9TWCvCpW+hY0NSBie40Oy2vflg3jIiuH+n/ITwlfrJYFcQ8fxf2/wV51Yi4jjoxyww+OE7ae9RPttDrtabhs5DibSs7aX+N9dyuquFWTji+tkQgikfwTrm8zZfIhGwOj1NcOP7PuMDuKquE/ec48/60NwXDPyVVuasVog6m3KHaEdFYyFg2RMO1iXTiZ/8Elp8BTH0ojJQKYIoSstryKpIzc6X/5/bdHLivRZTtg3Q7Rznl4L7BmOQKNbv0RhPrgHy4ucZnfreoj5HZnx+66to7t6aw96SYrupLaEh3NnUZHOwfApkp6xD+lQVXLmxVV7SqOQdKq4FSs0s= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(1800799024)(376014)(7416014)(82310400026)(11063799006)(6133799003)(18002099003)(22082099003)(56012099003)(4143699003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: dhT9Hh5/C7X6LgTcl0NIBT64i0Cb1627TCPKfSHIJVazG/qFCJkUPt5gcQMtD+LaeZM8+EzOHfZkZbmTrUr4K8TLedJ1KxPBn4qDUACBxFHOI/JCITSjVS2C+vO5s5VloC6KaB3LixJXWKz0ONlL+gmn6wdWoNmgK5pH9rWOiBOSyvlUacxFvDI2tunVTEty5BFleWC1EQK0+DY2QYH+9d3coP6qFR87yKPDCpj3MCYT5B0hOJJXXTLr2wbdzHTQ0AQmEY2uYFyzC5Ut5W2xHVhwZh+ExUxZxQhdr8hUT7170f9XDN1hd/hXt24iacL+H+oCf+QtcZ89H3CjuuV6eJAZRubjmhOnbMwFWOMIjzhvsvmf0FX8MMf3qZlUsBcNol+/0Me3nsOJqJJvwNH7NcixMzzxLnOibAIyOo+McEal9Tuq+I/KLqBxaTpPjEqt X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 May 2026 21:08:01.3997 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 686685da-7467-4663-d957-08deb77d0af1 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF0000009E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7671 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260521_140813_109722_92FF1287 X-CRM114-Status: GOOD ( 27.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 21, 2026 at 03:57:23PM -0500, Bjorn Helgaas wrote: > On Thu, May 21, 2026 at 01:34:20PM -0700, Nicolin Chen wrote: > > +bool pci_ats_required(struct pci_dev *pdev) > > +{ > > + if (!pci_ats_supported(pdev)) > > + return false; > > + > > + /* A VF inherits its PF's requirement for ATS function */ > > + if (pdev->is_virtfn) > > + pdev = pci_physfn(pdev); > > + > > + return pci_cxl_ats_required(pdev); > > I acked this before I saw this sashiko feedback, which looks like a > legit issue to me: > > Will this VF inheritance logic ever be reached? > > According to the PCIe SR-IOV specification (section 9.3.3.1), VFs do > not implement the ATS Extended Capability, which means pdev->ats_cap > is always 0 for VFs. > > Because of this, pci_ats_supported(pdev) will unconditionally return > false for any VF. This causes the function to return false before it > can ever reach the pdev->is_virtfn check. > > Could this prevent VFs from correctly enabling the ATS always on > feature and leave them unable to access host memory without > triggering IOMMU faults? > > (From https://sashiko.dev/#/patchset/cover.1779304390.git.nicolinc%40nvidia.com) > > I withdraw my ack for now until we figure out if it's a real issue. I did a bit of research here. The existing pci_enable_ats() checks: if (!pci_ats_supported(dev)) return -EINVAL; at the top, prior to: if (dev->is_virtfn) { pdev = pci_physfn(dev); if (pdev->ats_stu != ps) return -EINVAL; So, VF must *support* ATS (its ats_cap must be !0) so as to turn on ATS, instead of relying on the PF's ats_cap. IOW, Sashiko's comment "which means pdev->ats_cap is always 0 for VFs" is wrong. So, I kept the same order in this new pci_ats_required(). FWIW, I also did an inverted version and asked Sashiko to review: ==================================================================== > @@ -205,6 +205,52 @@ int pci_ats_page_aligned(struct pci_dev *pdev) [ ... ] > +bool pci_ats_required(struct pci_dev *pdev) > +{ > + /* A VF inherits its PF's requirement for ATS function */ > + if (pdev->is_virtfn) > + pdev = pci_physfn(pdev); > + > + if (!pci_ats_supported(pdev)) > + return false; This isn't a bug, but it looks like these two lines are indented with spaces instead of tabs. Also, since pdev is reassigned to pci_physfn(pdev) before checking ATS support, does this incorrectly check the ATS capability of the PF rather than the VF? If a VF has its ATS support explicitly disabled (for example, via PCIe quirks that set vf->ats_cap = 0), this check might bypass the VF's specific properties and incorrectly return true based on the PF's capabilities. Consequently, if a caller attempts to enable ATS on the VF by calling pci_enable_ats(), it will fail because pci_enable_ats() correctly checks pci_ats_supported() against the VF. Would it be better to evaluate pci_ats_supported() on the original pdev before reassigning it to the PF? ==================================================================== What would you like me to do, Bjorn? Nicolin