From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>, Joey Gouly <joey.gouly@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Will Deacon <will@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
Jonathan Corbet <corbet@lwn.net>, Shuah Khan <shuah@kernel.org>,
Oliver Upton <oupton@kernel.org>,
Dave Martin <Dave.Martin@arm.com>, Fuad Tabba <tabba@google.com>,
Ben Horgan <ben.horgan@arm.com>,
linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org,
Peter Maydell <peter.maydell@linaro.org>,
Eric Auger <eric.auger@redhat.com>
Subject: Re: [PATCH v10 04/30] arm64/fpsimd: Determine maximum virtualisable SME vector length
Date: Mon, 11 May 2026 11:32:56 +0100 [thread overview]
Message-ID: <agGwWE2hcj9O4EGu@J2N7QTR9R3.cambridge.arm.com> (raw)
In-Reply-To: <20260306-kvm-arm64-sme-v10-4-43f7683a0fb7@kernel.org>
On Fri, Mar 06, 2026 at 05:00:56PM +0000, Mark Brown wrote:
> As with SVE we can only virtualise SME vector lengths that are supported by
> all CPUs in the system, implement similar checks to those for SVE.
So far so good.
> Since unlike SVE there are no specific vector lengths that are
> architecturally required the handling is subtly different, we report a
> system where this happens with a maximum vector length of
> SME_VQ_INVALID.
I think something went wrong during copyediting here.
A system where *what* happens?
> Signed-off-by: Mark Brown <broonie@kernel.org>
> ---
> arch/arm64/include/asm/fpsimd.h | 2 ++
> arch/arm64/kernel/fpsimd.c | 21 ++++++++++++++++++++-
> 2 files changed, 22 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
> index e97729aa3b2f..0cd8a866e844 100644
> --- a/arch/arm64/include/asm/fpsimd.h
> +++ b/arch/arm64/include/asm/fpsimd.h
> @@ -69,6 +69,8 @@ static inline void cpacr_restore(unsigned long cpacr)
> #define ARCH_SVE_VQ_MAX ((ZCR_ELx_LEN_MASK >> ZCR_ELx_LEN_SHIFT) + 1)
> #define SME_VQ_MAX ((SMCR_ELx_LEN_MASK >> SMCR_ELx_LEN_SHIFT) + 1)
>
> +#define SME_VQ_INVALID (SME_VQ_MAX + 1)
Does using (SME_VQ_MAX + 1) for this make something easier than if we
used 0?
My thinking is that 0 will be easier/clearer overall, since we can write
checks of the form:
if (!info->max_virtualisable_vl) {
/* SME is not virtualisable */
}
... or:
if (some_vl <= max_virtualisable_vl) {
/* Check properties of a virtualisable VL */
}
... and there's less scope for error.
> +
> struct task_struct;
>
> extern void fpsimd_save_state(struct user_fpsimd_state *state);
> diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c
> index 2af0e0c5b9f4..49c050ef6db9 100644
> --- a/arch/arm64/kernel/fpsimd.c
> +++ b/arch/arm64/kernel/fpsimd.c
> @@ -1218,7 +1218,8 @@ void cpu_enable_sme(const struct arm64_cpu_capabilities *__always_unused p)
> void __init sme_setup(void)
> {
> struct vl_info *info = &vl_info[ARM64_VEC_SME];
> - int min_bit, max_bit;
> + DECLARE_BITMAP(tmp_map, SVE_VQ_MAX);
> + int min_bit, max_bit, b;
>
> if (!system_supports_sme())
> return;
> @@ -1249,12 +1250,30 @@ void __init sme_setup(void)
> */
> set_sme_default_vl(find_supported_vector_length(ARM64_VEC_SME, 32));
>
> + bitmap_andnot(tmp_map, info->vq_partial_map, info->vq_map,
> + SVE_VQ_MAX);
> +
> + b = find_last_bit(tmp_map, SVE_VQ_MAX);
> + if (b >= SVE_VQ_MAX)
> + /* All VLs virtualisable */
> + info->max_virtualisable_vl = sve_vl_from_vq(ARCH_SVE_VQ_MAX);
I don't think this is right.
This test tells us that all VLs implemented by boot CPUs are
virtualisable. That set of VLs doesn't necessarily include the
architectural maximum VL.
IIUC that's not a problem for KVM, since KVM enforces that a guest's
maximum VL is an implemented VL. However, this is a problem for
vec_verify_vq_map().
Consider the case where all boot CPUs support only 128-bit, but later we
try to online a CPU that supports 128-bit and 256-bit. That CPU will be
rejected by vec_verify_vq_map().
Note that this isn't broken for SVE today as sve_setup() follows this up
with:
if (info->max_virtualisable_vl > info->max_vl)
info->max_virtualisable_vl = info->max_vl;
... but that won't be sufficient for streaming mode VLs given there's no
guarantee that smaller streaming VLs are implemented.
> + else if (b == SVE_VQ_MAX - 1)
> + /* No virtualisable VLs */
> + info->max_virtualisable_vl = sve_vl_from_vq(SME_VQ_INVALID);
Similarly, I think this is broken for vec_verify_vq_map(). Consider a
case with two boot CPUs, where one boot CPU only supports 128-bit, and
the other boot cpu only supports 256-bit. If either CPU is hotplugged
out and then back in, it will be rejected by vec_verify_vq_map().
We don't have a similar problem for SVE since that's not architecturally
possible.
> + else
> + info->max_virtualisable_vl = sve_vl_from_vq(__bit_to_vq(b + 1));
This looks suspicious.
At this point we know that 'b' represents the smallest VL which is
partially supported. The next bit is almost never a power of two, is not
guaranteed to be an implemented VL, and is not guaranteed to be larger
than an implemented VL.
Imagine you have two CPUs:
* CPU x supports 128-bit.
* CPU y supports 128-bit and 512-bit.
The algorithm above will find 512-bit as the smallest partically
supported VL. For that, VQ==4 and b==12.
If max_virtualisable_vl is chosen as b+1, then that's b==13 and VQ==3,
which corresponds to a (not architecturally supported) 384-bit VL, which
is bigger than the architecturally-valid 256 bit VL that neither CPU
supports.
As with the other cases above, that's broken for vec_verify_vq_map(),
but I think KVM will gracefully handle this.
To solve all of the above, I think what we actually want to do is find
the largest uniformly implemented VL which is smaller than the smallest
partially implemented VL.
> pr_info("SME: minimum available vector length %u bytes per vector\n",
> info->min_vl);
> pr_info("SME: maximum available vector length %u bytes per vector\n",
> info->max_vl);
> pr_info("SME: default vector length %u bytes per vector\n",
> get_sme_default_vl());
> +
> + /* KVM decides whether to support mismatched systems. Just warn here: */
> + if (info->max_virtualisable_vl < info->max_vl ||
> + info->max_virtualisable_vl == sve_vl_from_vq(SME_VQ_INVALID))
> + pr_warn("SME: unvirtualisable vector lengths present\n");
If we used 0 instead of (SME_VQ_MAX + 1), this would just be:
if (info->max_virtualisable_vl < info->max_vl)
pr_warn(...);
As above, I think using 0 would be preferable.
Mark.
> }
>
> void sme_suspend_exit(void)
>
> --
> 2.47.3
>
next prev parent reply other threads:[~2026-05-11 10:33 UTC|newest]
Thread overview: 62+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-06 17:00 [PATCH v10 00/30] KVM: arm64: Implement support for SME Mark Brown
2026-03-06 17:00 ` [PATCH v10 01/30] arm64/sysreg: Update SMIDR_EL1 to DDI0601 2025-06 Mark Brown
2026-03-16 16:34 ` Catalin Marinas
2026-05-08 17:12 ` Mark Rutland
2026-05-09 0:43 ` Mark Brown
2026-05-11 10:40 ` Mark Rutland
2026-05-11 12:31 ` Mark Brown
2026-03-06 17:00 ` [PATCH v10 02/30] arm64/fpsimd: Update FA64 and ZT0 enables when loading SME state Mark Brown
2026-03-16 17:37 ` Catalin Marinas
2026-03-06 17:00 ` [PATCH v10 03/30] arm64/fpsimd: Decide to save ZT0 and streaming mode FFR at bind time Mark Brown
2026-03-16 17:42 ` Catalin Marinas
2026-03-06 17:00 ` [PATCH v10 04/30] arm64/fpsimd: Determine maximum virtualisable SME vector length Mark Brown
2026-03-16 17:44 ` Catalin Marinas
2026-03-18 17:29 ` Jean-Philippe Brucker
2026-05-11 10:32 ` Mark Rutland [this message]
2026-05-11 12:42 ` Mark Brown
2026-03-06 17:00 ` [PATCH v10 05/30] KVM: arm64: Pay attention to FFR parameter in SVE save and load Mark Brown
2026-03-18 17:30 ` Jean-Philippe Brucker
2026-03-06 17:00 ` [PATCH v10 06/30] KVM: arm64: Pull ctxt_has_ helpers to start of sysreg-sr.h Mark Brown
2026-03-18 17:31 ` Jean-Philippe Brucker
2026-03-06 17:00 ` [PATCH v10 07/30] KVM: arm64: Move SVE state access macros after feature test macros Mark Brown
2026-03-18 17:32 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 08/30] KVM: arm64: Rename SVE finalization constants to be more general Mark Brown
2026-03-18 17:33 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 09/30] KVM: arm64: Define internal features for SME Mark Brown
2026-03-18 17:44 ` Jean-Philippe Brucker
2026-03-18 17:50 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 10/30] KVM: arm64: Rename sve_state_reg_region Mark Brown
2026-03-18 17:46 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 11/30] KVM: arm64: Store vector lengths in an array Mark Brown
2026-03-18 17:48 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 12/30] KVM: arm64: Factor SVE code out of fpsimd_lazy_switch_to_host() Mark Brown
2026-03-18 17:49 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 13/30] KVM: arm64: Document the KVM ABI for SME Mark Brown
2026-03-18 17:51 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 14/30] KVM: arm64: Implement SME vector length configuration Mark Brown
2026-03-18 17:53 ` Jean-Philippe Brucker
2026-04-23 18:34 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 15/30] KVM: arm64: Support SME control registers Mark Brown
2026-03-18 17:54 ` Jean-Philippe Brucker
2026-05-08 17:20 ` Mark Rutland
2026-05-11 14:17 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 16/30] KVM: arm64: Support TPIDR2_EL0 Mark Brown
2026-03-18 17:55 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 17/30] KVM: arm64: Support SME identification registers for guests Mark Brown
2026-03-18 17:27 ` Jean-Philippe Brucker
2026-03-06 17:01 ` [PATCH v10 18/30] KVM: arm64: Support SME priority registers Mark Brown
2026-03-06 17:01 ` [PATCH v10 19/30] KVM: arm64: Provide assembly for SME register access Mark Brown
2026-03-06 17:01 ` [PATCH v10 20/30] KVM: arm64: Support userspace access to streaming mode Z and P registers Mark Brown
2026-03-06 17:01 ` [PATCH v10 21/30] KVM: arm64: Flush register state on writes to SVCR.SM and SVCR.ZA Mark Brown
2026-03-06 17:01 ` [PATCH v10 22/30] KVM: arm64: Expose SME specific state to userspace Mark Brown
2026-03-06 17:01 ` [PATCH v10 23/30] KVM: arm64: Context switch SME state for guests Mark Brown
2026-03-06 17:01 ` [PATCH v10 24/30] KVM: arm64: Handle SME exceptions Mark Brown
2026-03-06 17:01 ` [PATCH v10 25/30] KVM: arm64: Expose SME to nested guests Mark Brown
2026-03-06 17:01 ` [PATCH v10 26/30] KVM: arm64: Provide interface for configuring and enabling SME for guests Mark Brown
2026-03-06 17:01 ` [PATCH v10 27/30] KVM: arm64: selftests: Remove spurious check for single bit safe values Mark Brown
2026-03-06 17:01 ` [PATCH v10 28/30] KVM: arm64: selftests: Skip impossible invalid value tests Mark Brown
2026-03-24 14:54 ` Ben Horgan
2026-03-24 14:56 ` Mark Brown
2026-03-06 17:01 ` [PATCH v10 29/30] KVM: arm64: selftests: Add SME system registers to get-reg-list Mark Brown
2026-03-06 17:01 ` [PATCH v10 30/30] KVM: arm64: selftests: Add SME to set_id_regs test Mark Brown
2026-04-02 21:12 ` (subset) [PATCH v10 00/30] KVM: arm64: Implement support for SME Catalin Marinas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=agGwWE2hcj9O4EGu@J2N7QTR9R3.cambridge.arm.com \
--to=mark.rutland@arm.com \
--cc=Dave.Martin@arm.com \
--cc=ben.horgan@arm.com \
--cc=broonie@kernel.org \
--cc=catalin.marinas@arm.com \
--cc=corbet@lwn.net \
--cc=eric.auger@redhat.com \
--cc=joey.gouly@arm.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.linux.dev \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=maz@kernel.org \
--cc=oupton@kernel.org \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=shuah@kernel.org \
--cc=suzuki.poulose@arm.com \
--cc=tabba@google.com \
--cc=will@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox