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[34.124.234.44]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2baf1d26968sm102835425ad.16.2026.05.11.06.22.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 May 2026 06:22:29 -0700 (PDT) Date: Mon, 11 May 2026 13:22:23 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: Robin Murphy , Jason Gunthorpe , Will Deacon , Joerg Roedel , Jean-Philippe Brucker , Catalin Marinas , =?utf-8?Q?Miko=C5=82aj?= Lenczewski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] iommu/arm-smmu-v3-sva: Enable Hardware Access and Hardware Dirty bits Message-ID: References: <20260503135413.1108138-1-nicolinc@nvidia.com> <20260508123550.GB9254@nvidia.com> <4e129891-2f52-4bac-8e33-1fdde42fd29a@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260511_062231_925685_203ACD3C X-CRM114-Status: GOOD ( 22.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, May 09, 2026 at 12:56:57AM -0700, Nicolin Chen wrote: > On Fri, May 08, 2026 at 03:24:32PM +0100, Robin Murphy wrote: > > On 2026-05-08 2:57 pm, Pranjal Shrivastava wrote: > > > I see, so IIUC, you mean if IS_ENABLED(CONFIG_ARM64_HW_AFDBM) but CPU > > > doesn't enable HTTU, it is perfectly safe to let the SMMU do HTT updates, > > > Since the fault handlers are already expecting HW-triggered updates? > > > > > > Which means our check would be something like: > > > > > > if (IS_ENABLED(CONFIG_ARM64_HW_AFDBM) { > > > if (smmu->features & FEAT_HA) > > > ... > > > } > > > > > > instead of cpu_has_hw_af()? > > > > Hmm, looking closer, cpu_has_hw_af() is the thing which actually influences > > mm behaviour (via arch_has_hw_pte_young and arch_wants_old_prefaulted_pte), > > and that can still be false at runtime if ARM64_HW_AFDBM is enabled but any > > CPU doesn't support HAFDBS, so perhaps you were right the first time :) > > IIUIC, v2 should be: > > + /* > + * Enable Hardware Access and Dirty updates (DBM) if supported by > + * both the SMMU and the CPU. It is unsafe to enable SMMU's HTTU, > + * if the CPU does not support it as it bypasses mm page aging. > + */ > + if (cpu_has_hw_af()) { Ack, yes. IMO, this is the correct system-wide gate. > + if (master->smmu->features & ARM_SMMU_FEAT_HA) > + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA); > + if (master->smmu->features & ARM_SMMU_FEAT_HD) > + target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HD); > + } > Thanks, Praan