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Fri, 15 May 2026 18:25:10 +0800 (CST) Date: Fri, 15 May 2026 18:25:09 +0800 From: Peter Chen To: Krzysztof Kozlowski Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, gregkh@linuxfoundation.org, pawell@cadence.com, rogerq@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org, cix-kernel-upstream@cixtech.com, linux-arm-kernel@lists.infradead.org, arnd@arndb.de Subject: Re: [PATCH 3/4] dt-bindings: usb: add CIX Sky1 Cadence USB3 controller Message-ID: References: <20260511024244.981941-1-peter.chen@cixtech.com> <20260511024244.981941-4-peter.chen@cixtech.com> <20260515-dynamic-archetypal-reindeer-dc6dd5@quoll> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260515-dynamic-archetypal-reindeer-dc6dd5@quoll> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CD:EE_|OS8PR06MB7324:EE_ X-MS-Office365-Filtering-Correlation-Id: 5b45c61e-3c23-4964-6a96-08deb26c3f53 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|1800799024|376014|4143699003|18002099003|22082099003|56012099003|3023799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: UKZg6nyDGfS+exr+DlMZhojIPloRYtKkW1ZloFGGgrw+8BEGU3I2S5PB9Wquskk7BryGnTiqHfwGMdx6it7z9T47b7mCXPO7Rp3ZAPe2TZ2MRUhpBYaeFtth5n7eHiK4vfbDRz5KLO/oGxyNB9DMV3ZCVCmwFUtNeD7gQe/rcniIhktygSIG3JmN7Vm6iQST3Ri6c0+F+Gp55TnQE7Za0Rilxb/t5+wR8UjKbR7TxSNCVn0mria5eWOf3r/oCjo8R5rUZMNSAXjZGaF0nTk3FwmEj+X7qw0gwC3d24X2eNlwhrSsosFhpcF1Pp5dWN1Jh/SgDsBfJa+08eqDu+MwoDkbC0OOMsjxNX4ZriHR5LvbR4xZpRyniR4PH574c39WcWWTvgTBki+lGlb4g/gTMRJ7O3Vs3QnQTDDTe+W4j8m/QXK1j/rFGZD6QmIoT2hN X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 May 2026 10:25:11.8203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5b45c61e-3c23-4964-6a96-08deb26c3f53 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CD.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS8PR06MB7324 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260515_032523_768313_908F1978 X-CRM114-Status: GOOD ( 25.63 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 26-05-15 09:54:10, Krzysztof Kozlowski wrote: > EXTERNAL EMAIL > > On Mon, May 11, 2026 at 10:42:43AM +0800, Peter Chen wrote: > > Add a binding for the CIX Sky1 integration of the Cadence USBSSP DRD > > controller. The schema documents the glue register window, clocks, > > resets, interrupts and S5 system controller phandle. > > > > Signed-off-by: Peter Chen > > --- > > .../bindings/usb/cix,sky1-cdns3.yaml | 151 ++++++++++++++++++ > > Why are you mixing USB patches with DTS in one patchset? Don't. In this series, the 1st patch is the IP core driver changes (export APIs for glue layer use), and the second glue layer patch is the user for new adding APIs. Normally, we combine dt-binding, driver (glue layer) and DTS changes at one patch series. It is much like below submission: https://lore.kernel.org/all/20250318-dwc3-refactor-v5-0-90ea6e5b3ba4@oss.qualcomm.com/ > > > 1 file changed, 151 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/usb/cix,sky1-cdns3.yaml > > > > diff --git a/Documentation/devicetree/bindings/usb/cix,sky1-cdns3.yaml b/Documentation/devicetree/bindings/usb/cix,sky1-cdns3.yaml > > new file mode 100644 > > index 000000000000..23d82d8cc9bc > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/usb/cix,sky1-cdns3.yaml > > Complete mess of filename. There is no such compatible. Will rename to cix,sky1-usb3.yaml matching the compatible in v2. > > > + > > +properties: > > + compatible: > > + items: > > + - const: cix,sky1-usb3 > > + - const: cix,cdns-usb3 > > I don't understand the fallback compatible. You claim this device is > called EXACTLY like vendor cdns? Nope, you SoC specific compatibles. The intent was to express "this is a Cadence USB3 IP integrated on a CIX SoC" but "cix,cdns-usb3" is wrong. Will drop the fallback compatible in v2, and there is only one compatible here. > > > > + > > + reg: > > + items: > > + - description: OTG controller registers > > + - description: Device controller registers > > + - description: XHCI host controller registers > > + - description: Sky1 USB glue registers > > + > > + reg-names: > > + items: > > + - const: otg > > + - const: dev > > + - const: xhci > > Wrong order, look at cdns,usb3 schema. Right, will reorder to match cdns,usb3: otg, xhci, dev in v2. > > > + - const: glue > > + > > + interrupts: > > + items: > > + - description: XHCI host controller interrupt > > + - description: Device controller interrupt > > + - description: OTG/DRD controller interrupt > > + - description: Wakeup interrupt > > + > > + interrupt-names: > > + items: > > + - const: host > > + - const: peripheral > > + - const: otg > > + - const: wakeup > > + > > + clocks: > > + items: > > + - description: Start-of-frame clock > > + - description: AXI bus clock > > + - description: Low-power mode clock > > + - description: APB register interface clock > > + > > + clock-names: > > + items: > > + - const: sof > > + - const: aclk > > + - const: lpm > > + - const: pclk > > + > > + resets: > > + items: > > + - description: APB register reset > > + - description: Controller reset > > + > > + reset-names: > > + items: > > + - const: prst > > apb > > > + - const: rst > > controller or core Will rename to: prst -> apb, rst -> core. > > > + > > + cix,syscon-usb: > > + $ref: /schemas/types.yaml#/definitions/phandle > > + description: > > + Phandle to the Sky1 S5 system controller used to program USB mode > > + strap controls. > > + > > + dma-coherent: true > > + > > + maximum-speed: > > + enum: [super-speed-plus, super-speed, high-speed, full-speed] > > Why isn't this deducible from the compatible? It is the common compatible (Documentation/devicetree/bindings/usb/usb.yaml) I will delete it, and add $ref: usb.yaml#. > > > + > > + phys: > > + minItems: 1 > > + maxItems: 2 > > No, this is not flexible. At Sky1 SoC, some USB controllers connect to both USB3 and USB2 PHYs, the others only connect USB2 PHY for dedicated USB2-only port. > > > + > > + phy-names: > > + minItems: 1 > > + maxItems: 2 > > + items: > > + anyOf: > > + - const: cdns3,usb2-phy > > + - const: cdns3,usb3-phy > > Drop all this and define standard names. Will use standard names: usb2-phy, usb3-phy in v2. > > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - interrupts > > + - interrupt-names > > + - clocks > > + - clock-names > > + - resets > > + - reset-names > > + - cix,syscon-usb > > phys should be required, no? Yes, will add phys and phy-names to required in v2. -- Best regards, Peter