From: Brian Masney <bmasney@redhat.com>
To: Joey Lu <a0987203069@gmail.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org, ychuang3@nuvoton.com,
schung@nuvoton.com, yclu4@nuvoton.com,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/3] clk: nuvoton: ma35d1: fix ignored div_u64 return values in PLL freq calculation
Date: Tue, 19 May 2026 10:51:57 -0400 [thread overview]
Message-ID: <agx5DSrHkmKeEejN@redhat.com> (raw)
In-Reply-To: <20260513055626.1070533-2-a0987203069@gmail.com>
On Wed, May 13, 2026 at 01:56:24PM +0800, Joey Lu wrote:
> div_u64() does not modify its argument in place; the return value must
> be assigned. Both ma35d1_calc_smic_pll_freq() and ma35d1_calc_pll_freq()
> called div_u64() and discarded the result, leaving pll_freq holding the
> undivided product and thus returning a frequency orders of magnitude too
> high.
>
> Fixes: 691521a367cf ("clk: nuvoton: Add clock driver for ma35d1 clock controller")
> Signed-off-by: Joey Lu <a0987203069@gmail.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
next prev parent reply other threads:[~2026-05-19 14:52 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-13 5:56 [PATCH v2 0/3] clk: nuvoton: ma35d1: fix PLL frequency calculation Joey Lu
2026-05-13 5:56 ` [PATCH v2 1/3] clk: nuvoton: ma35d1: fix ignored div_u64 return values in PLL freq calculation Joey Lu
2026-05-19 14:51 ` Brian Masney [this message]
2026-05-13 5:56 ` [PATCH v2 2/3] clk: nuvoton: ma35d1: fix PLL_CTL1_FRAC bit field width and fractional calc Joey Lu
2026-05-19 14:53 ` Brian Masney
2026-05-20 2:14 ` Joey Lu
2026-05-13 5:56 ` [PATCH v2 3/3] clk: nuvoton: ma35d1: fix ma35d1_clk_pll_determine_rate logic Joey Lu
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