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Mon, 25 May 2026 13:05:38 -0700 Date: Mon, 25 May 2026 13:05:36 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , , , , "Joerg Roedel" , Will Deacon , Bjorn Helgaas , David Woodhouse , Lu Baolu , Robin Murphy , "Suravee Suthikulpanit" , Jason Gunthorpe , David Matlack , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , Mostafa Saleh Subject: Re: [PATCH v4 3/5] iommu/arm-smmu-v3: Fix ATS state tracking Message-ID: References: <20260525184347.4059549-1-praan@google.com> <20260525184347.4059549-4-praan@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260525184347.4059549-4-praan@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022575:EE_|SA1PR12MB8699:EE_ X-MS-Office365-Filtering-Correlation-Id: 6ce48b7e-9ebe-4291-2da9-08deba9904c9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|82310400026|36860700016|1800799024|4143699003|11063799006|56012099003|18002099003|22082099003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Gxcs462pQM9dgXEUoI8+3tbLHj2Ou94bAqhHOMrWuxhlUVbQ5Hf3P25Vby+OX0Bt5B4QIywK+zkWjZn2j+9Xq5F5ieFxI/exIbFfbJtg3UUMNqB8N0KPzhn1PPnV+kf/q5R6PmCILFhXqJWeA6jEZvYI7BYWZuqyK+WSoLoc9yHNc/8qLPMBgFg1mtq8BTTIHktM+okTBz5cu74yEdFCI4IRLFz4+a9ATQ/Uy4GGnhziDVhjylNhEOTm7LEnXLbAxmlV9z34caFEg/fkPnXreXOMxMi/O4g1Rg9QyYFeYqO6LYazpybyMaQYOEGl7StOKucc39+nwcxRDsb8FU+5E/8BdC406En0LB3osSkakcDLMzSBbfzfYzksChFD+iDW8w7g/SnJcYuilfrSxQ5Lk6q2wtsdjhv506n4LphjMCoPFJM/md1hp/9rTqH2a5fE X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 25 May 2026 20:05:50.4341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6ce48b7e-9ebe-4291-2da9-08deba9904c9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022575.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB8699 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260525_130557_026903_B4E6FE09 X-CRM114-Status: GOOD ( 17.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 25, 2026 at 06:43:45PM +0000, Pranjal Shrivastava wrote: > @@ -3065,8 +3065,14 @@ static void arm_smmu_enable_ats(struct arm_smmu_master *master) > * ATC invalidation of PASID 0 causes the entire ATC to be flushed. > */ > arm_smmu_atc_inv_master(master, IOMMU_NO_PASID); > - if (pci_enable_ats(pdev, stu)) > - dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); > + > + /* > + * Any failure at this point is a kernel bug. pci_ats_supported() > + * and pci_prepare_ats() have already verified the hardware capability > + * and programmed the STU. Thus, pci_enable_ats() should not fail here. Nits: - WARN usually indicates a kernel bug already. - pci_prepare_ats() covers pci_ats_supported(). /* * As pci_prepare_ats() have already verified the hardware capability * and programmed the STE, pci_enable_ats() should not fail here. */ > @@ -4264,9 +4270,16 @@ static struct iommu_device *arm_smmu_probe_device(struct device *dev) > master->stall_enabled = true; > > if (dev_is_pci(dev)) { > - unsigned int stu = __ffs(smmu->pgsize_bitmap); > + struct pci_dev *pdev = to_pci_dev(dev); > > - pci_prepare_ats(to_pci_dev(dev), stu); > + if (pci_ats_supported(pdev)) { > + unsigned int stu = __ffs(smmu->pgsize_bitmap); > + int ret; > + > + ret = pci_prepare_ats(pdev, stu); > + if (ret) > + return ERR_PTR(ret); > + } Again, pci_prepare_ats() covers pci_ats_supported(). So, the check is redundant. Instead, it should check arm_smmu_ats_supported(). By the way, this would conflict into my series: https://lore.kernel.org/linux-iommu/18bb6f421b3be891caa8f1fb50f3a4d56b52d5be.1779392420.git.nicolinc@nvidia.com/ It would be nicer to have an arm_smmu_master_prepare_ats() so that both series would have a common ground; mine would be just adding some additional lines if your series goes in first. Thanks Nicolin