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[34.124.234.44]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-36bbe1f9377sm46400a91.13.2026.05.28.14.57.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 May 2026 14:57:10 -0700 (PDT) Date: Thu, 28 May 2026 21:57:04 +0000 From: Pranjal Shrivastava To: Nicolin Chen Cc: iommu@lists.linux.dev, Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Daniel Mentz , Ashish Mhetre , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v7 05/11] iommu/arm-smmu-v3: Cache and restore MSI config Message-ID: References: <20260527221407.1756491-1-praan@google.com> <20260527221407.1756491-6-praan@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260528_145712_930137_5C8E71E0 X-CRM114-Status: GOOD ( 22.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 28, 2026 at 11:36:06AM -0700, Nicolin Chen wrote: > On Wed, May 27, 2026 at 10:14:01PM +0000, Pranjal Shrivastava wrote: > > The SMMU's MSI configuration registers (*_IRQ_CFGn) containing target > > address, data and memory attributes lose their state when the SMMU is > > powered down. We'll need to cache and restore their contents to ensure > > that MSIs work after the system resumes. > > > > To address this, cache the original `msi_msg` within the `msi_desc` > > when the configuration is first written by `arm_smmu_write_msi_msg`. > > This primarily includes the target address and data since the memory > > attributes are fixed. > > > > Introduce a new helper `arm_smmu_resume_msis` which will later be called > > during the driver's resume callback. The helper would retrieve the > > cached MSI message for each relevant interrupt (evtq, gerr, priq) via > > get_cached_msi_msg & re-config the registers via arm_smmu_write_msi_msg. > > > > Signed-off-by: Pranjal Shrivastava > > Reviewed-by: Nicolin Chen > > > +static void arm_smmu_resume_msi(struct arm_smmu_device *smmu, > > + unsigned int irq, const char *name) > > +{ > > + struct msi_desc *desc; > > + struct msi_msg msg; > > + > > + if (!irq) > > + return; > > + > > + desc = irq_get_msi_desc(irq); > > + if (!desc) { > > + dev_err(smmu->dev, "Failed to resume msi: %s", name); > > + return; > > + } > > + > > + get_cached_msi_msg(irq, &msg); > > I wonder if we could use __get_cached_msi_msg() since we got desc? We could've (and that's a nice suggestion), but unfortunately it (__get_cached_msi_msg) is not exported via EXPORT_SYMBOL_GPL() :( We could break modular builds as CONFIG_ARM_SMMU_V3 is tristate. Let me know if you have a strong preference about exporting it, we can add a patch in the next versions. Thanks, Praan