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Fri, 29 May 2026 14:51:53 -0700 Date: Fri, 29 May 2026 14:51:52 -0700 From: Nicolin Chen To: Pranjal Shrivastava CC: , , , , "Joerg Roedel" , Will Deacon , Bjorn Helgaas , David Woodhouse , Lu Baolu , Robin Murphy , "Suravee Suthikulpanit" , Jason Gunthorpe , David Matlack , Samiullah Khawaja , Daniel Mentz , Pasha Tatashin , Mostafa Saleh Subject: Re: [PATCH v6 4/6] iommu/arm-smmu-v3: Standardize ATS enablement failure reporting Message-ID: References: <20260529111208.387412-1-praan@google.com> <20260529111208.387412-5-praan@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260529111208.387412-5-praan@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB75:EE_|CH3PR12MB8403:EE_ X-MS-Office365-Filtering-Correlation-Id: 3862e659-4dbb-45c4-5c13-08debdcc8db0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|7416014|1800799024|82310400026|13003099007|6133799003|11063799006|56012099006|18002099003|22082099003|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 7uzzJPdOgp5ycc7IWCuep/0R/8RhgoLPnA60YFepj94Cx3bipTyaNkVLSH5RBSizbIjBlVXdQZlpfY8NVcNlP9mMHUVBV/BeGMNTbMdptxBuLRFcbSZbqhBAJqUTtEszxDySWwv9u5TyQNwAPeIuZOajmMVzqKMeHmb20BLhUpAuJWgmGFudLkZ+1cG0NnuptXm+RDwR8RIeIsLn6A8EaTooGugOhxTZvtLf+WohB5AEMYqxIYsBxlNzI7gvrz8HEcdJqpSM/h3bR14fNkoaK/ajc1n416h+vqELYmPDDpE1K2pyoHvN/tqPxrmiCMHI417DD3cWZrQuj6kH6IiWl8JHBzqV55zuTuQBMQeFONL2z7tuNM/qYmtaL+qYt7ncLltMcCxa8hhXK1cPyWCUUS/0ayaOyjjnKwX8d0slO6g9nmShQ4piqpy2yGw2zSc2 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 May 2026 21:52:17.9385 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3862e659-4dbb-45c4-5c13-08debdcc8db0 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB75.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8403 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260529_145225_679469_06B23882 X-CRM114-Status: GOOD ( 23.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, May 29, 2026 at 11:12:06AM +0000, Pranjal Shrivastava wrote: > The SMMUv3 driver currently has a two-phase commit in its ATS enablement > flow. During arm_smmu_attach_prepare(), it predicts whether ATS will be > enabled using arm_smmu_ats_supported() and accordingly increments > nr_ats_masters and merges ATS invalidations into the domain's invs array. > > However, the actual hardware enablement via pci_enable_ats() happens > later in arm_smmu_attach_commit(). If this call to pci_enable_ats fails, > the SMMU driver's ATS state tracking remains polluted, i.e., the driver > tracks ATS as enabled on a master that is not actually using it. This > leads to an incorrect nr_ats_masters and triggers a warning in the PCI > core during detach: > > 1 [ 127.925080] ------------[ cut here ]------------ > 2 [ 127.925084] WARNING: drivers/pci/ats.c:132 at pci_disable_ats+0x94/0xa8 > 3 ... > 4 [ 128.068169] Call trace: > 5 [ 128.070603] pci_disable_ats+0x94/0xa8 (P) > 6 [ 128.074688] arm_smmu_attach_prepare+0x104/0x310 > 7 [ 128.079292] arm_smmu_attach_dev_ste+0x128/0x1e0 > > The issue was exposed under heavy load when running a VFIO-based DMA > map stress test (iova_stress). > > Following the addition of the arm_smmu_master_prepare_ats() [1] helper during > device probe, failable ATS configuration (STU setup) is now handled early > during probe. This ensures that any master reaching the attach phase is > guaranteed to have a valid ATS configuration. > > Update arm_smmu_enable_ats() to use the WARN() macro for any > subsequent enablement failures during the commit phase. Since probe > checks now preclude software configuration errors, any failure here is > considered a kernel bug. The commit message feels like mixing a stale background and the real requirement (based on the latest code line). Could that DMA map stress test still trigger the WARN_ON in pci_disable_ats(), after having arm_smmu_master_prepare_ats()? It'd be nicer if the writing can be simplified a bit. > arm_smmu_atc_inv_master(master, IOMMU_NO_PASID); > - if (pci_enable_ats(pdev, stu)) > - dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); > + > + /* > + * Any failure at this point is a kernel bug. pci_ats_supported() > + * and pci_prepare_ats() have already verified the hardware capability > + * and programmed the STU. Thus, pci_enable_ats() should not fail here. > + */ The patch that removes pci_ats_supported() from pci_prepare_ats() is dropped in this v6. So, my previous comments may stay true and the two lines can be enough? /* * As pci_prepare_ats() have already verified the hardware capability * and programmed the STE, pci_enable_ats() should not fail here. */ > + WARN(pci_enable_ats(pdev, stu), > + "Failed to enable ATS (STU %zu)\n", stu); https://sashiko.dev/#/patchset/20260529111208.387412-1-praan%40google.com Please check Sashiko review (for other patches in this series too). I think it'd be cleaner to just have: - if (pci_enable_ats(pdev, stu)) + if (WARN_ON(pci_enable_ats(pdev, stu))) Nicolin