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[34.142.255.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c16629d042sm216609875ad.60.2026.06.09.03.12.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Jun 2026 03:12:22 -0700 (PDT) Date: Tue, 9 Jun 2026 10:12:17 +0000 From: Pranjal Shrivastava To: Daniel Mentz Cc: iommu@lists.linux.dev, Will Deacon , Joerg Roedel , Robin Murphy , Jason Gunthorpe , Mostafa Saleh , Nicolin Chen , Ashish Mhetre , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v8 09/12] iommu/arm-smmu-v3: Implement pm_runtime & system sleep ops Message-ID: References: <20260601215909.3958732-1-praan@google.com> <20260601215909.3958732-10-praan@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260609_031224_641462_C79EF2C1 X-CRM114-Status: GOOD ( 20.60 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, Jun 07, 2026 at 02:53:24PM -0700, Daniel Mentz wrote: > On Mon, Jun 1, 2026 at 2:59 PM Pranjal Shrivastava wrote: > > @@ -4898,6 +4939,21 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) > > if (is_kdump_kernel()) > > enables &= ~(CR0_EVTQEN | CR0_PRIQEN); > > > > + /* > > + * While the SMMU was suspended, concurrent CPU threads may have > > + * updated in-memory structures (such as STEs, CDs, and PTEs). > > + * Any invalidations corresponding to those updates were safely > > + * elided because the command queue was stopped (STOP_FLAG == 1). > > + * > > + * Since the reset invalidate-all commands above have fully cleared > > + * the HW TLBs and config caches, the SMMU will fetch these descriptors > > + * directly from RAM as soon as translation is enabled. > > + * > > + * Add a memory barrier to collect all prior RAM writes to ensure the > > + * SMMU sees a consistent view of memory before translation is enabled. > > + */ > > + smp_mb(); > > I'm not convinced that this is necessary. I understand that the write > to smmu->cmdq.q.llq.atomic.prod needs to be ordered before setting > CR0_SMMUEN in ARM_SMMU_CR0. However, this ordering requirement appears > to already be met by the dma_wmb() in arm_smmu_cmdq_issue_cmdlist. > Could you provide an example of a scenario that might fail if this > smp_mb() were removed? Agreed. The first dma_wmb() in the issue_cmdlist will handle this. We don't need this smp_mb(); I'll add a note as specified in [1] Thanks, Praan [1] https://lore.kernel.org/all/aiflaI4svEJvZbsC@google.com/