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Mon, 15 Jun 2026 12:30:53 -0700 (PDT) Received: from geday ([189.115.92.220]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1384b97570asm10735958c88.12.2026.06.15.12.30.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 12:30:53 -0700 (PDT) Date: Mon, 15 Jun 2026 16:30:38 -0300 From: Geraldo Nascimento To: Shawn Lin , Dragan Simic Cc: linux-rockchip@lists.infradead.org, Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v6 3/3] PCI: rockchip: drive at 2.5 GT/s, error other speeds Message-ID: References: <4ac5cd7d2271df375ed6307f5c394247721395d9.1781207474.git.geraldogabriel@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4ac5cd7d2271df375ed6307f5c394247721395d9.1781207474.git.geraldogabriel@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260615_123055_292421_D3A8401D X-CRM114-Status: GOOD ( 24.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, On Thu, Jun 11, 2026 at 05:04:22PM -0300, Geraldo Nascimento wrote: > Configure the core to be driven at 2.5 GT/s Link Speed and ignore > any other speed with a warning. Also drop the 5.0 GT/s Link Speed > defines from Rockchip PCIe header. > > The reason is that Shawn Lin from Rockchip has reiterated that there > may be danger of "catastrophic failure" in using their PCIe with > 5.0 GT/s speeds. > > While Rockchip has done so informally without issuing a proper errata, > and the particulars are thus unknown, this may cause data loss or > worse. > > This change is corroborated by RK3399 official datasheet [1], which > states maximum link speed for this platform is 2.5 GT/s. > > [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf > > Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") > Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ > Cc: stable@vger.kernel.org > Reported-by: Dragan Simic > Reported-by: Shawn Lin > Signed-off-by: Geraldo Nascimento > --- > drivers/pci/controller/pcie-rockchip.c | 16 +++++++++------- > drivers/pci/controller/pcie-rockchip.h | 3 --- > 2 files changed, 9 insertions(+), 10 deletions(-) > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > index 0f88da3788054..5a2876d7c8547 100644 > --- a/drivers/pci/controller/pcie-rockchip.c > +++ b/drivers/pci/controller/pcie-rockchip.c > @@ -66,8 +66,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) > } > > rockchip->link_gen = of_pci_get_max_link_speed(node); > - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) > - rockchip->link_gen = 2; > + if (rockchip->link_gen < 0 || rockchip->link_gen >= 2) { > + rockchip->link_gen = 1; > + dev_warn(dev, "invalid max-link-speed, limited to 2.5 GT/s\n"); > + } > > for (i = 0; i < ROCKCHIP_NUM_PM_RSTS; i++) > rockchip->pm_rsts[i].id = rockchip_pci_pm_rsts[i]; > @@ -147,12 +149,12 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) > goto err_exit_phy; > } > > + /* 5.0 GT/s may cause catastrophic failure for this core */ > if (rockchip->link_gen == 2) > - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, Sashiko caught unreachable dead code rightfully here. It looks like I had got it right in v4 and then the fix regressed. Will address this for v7 after I get more comments. Thanks, Geraldo Nascimento