From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BA883CD98EE for ; Wed, 17 Jun 2026 09:17:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:References:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ZnXuxdsvCZXi+yhcRRlP0nnKlUJzsEw2xOj6/CVvJuY=; b=sUMbO7c7VXuP3+zJV10KtaRMSb oI7FjSbVa6Z8oNQEeIhYSB1LqaN7rfqaIfPC9Bdqa7qpi1l3FLhs2I5MxpNvR4t3EMR9WetnuvKCV v/d1XTEtjVIPRn6Y6ZOJT53cXXEP32S55+8DkwUKlCf+7OlF9JqYmL1ii8n77ps9Z72HmUioDixR8 JTXNgq81BTenNbAr7YjMrI0doQz+imxW1UXyxCJ/vXaAfptrZs6K6fGGDI/lZfHYYfagkDAFUXLya rDU2WKC5pfUtY5jb7DkTiER1Pckphpdj9N7psHmAXSep7aVxTrUk5WMYPJ3Dw3c4E1pLYaa/iS2fc Dg+NXdNQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wZmOi-0000000GwbZ-1w0p; Wed, 17 Jun 2026 09:17:24 +0000 Received: from tor.source.kernel.org ([2600:3c04:e001:324:0:1991:8:25]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wZmOh-0000000GwbM-2DB8; Wed, 17 Jun 2026 09:17:23 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by tor.source.kernel.org (Postfix) with ESMTP id 89D27600AA; Wed, 17 Jun 2026 09:17:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id B3B671F000E9; Wed, 17 Jun 2026 09:17:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1781687842; bh=ZnXuxdsvCZXi+yhcRRlP0nnKlUJzsEw2xOj6/CVvJuY=; h=Date:From:To:Cc:Subject:References:In-Reply-To; b=Tc2o8afQpKiwso4i+pUMbegXm9w4FdsldOJEIycWlQuBKzvzKP/80uB25ERY7H9to rlTBV9HS2My1rfz+o5ejfrZv7pxmZVA/3VLl0xw+1VpT9WdMAaKAWs2fQlF642MRWp R0fZrndsiKF6U6XD4tFD/tYT8DBjO/HryBTGwlRuKeptvYqTlfyqRpuLmqBTa3OAwh 9j9K164Ij7Ja+gPqjqgK4f0zErjFpRDU0dtYxFsvmZ3zYO7nwHGO0sOdRGvdsT3kqX /nGioXXdZFVhPWbAzswPyQ096Fsff7VYQk1V1GJ3Rz20/AAqQwlk9iPVEJZVPjwkyo zcJ2kCDF+XuZQ== Date: Wed, 17 Jun 2026 11:17:20 +0200 From: Lorenzo Bianconi To: Wayen Yan Cc: netdev@vger.kernel.org, nbd@nbd.name, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: Re: [PATCH net] net: airoha: Fix TX scheduler queue mask loop upper bound Message-ID: References: <178166704952.2212140.11002626760717132754@gmail.com> <178168650178.2224380.3950331731013129336@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="VyUTMvxzWiaGc/iq" Content-Disposition: inline In-Reply-To: <178168650178.2224380.3950331731013129336@gmail.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --VyUTMvxzWiaGc/iq Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > On Tue, Jun 17, 2026, Lorenzo Bianconi wrote: > > Even if the current codebase supports just AIROHA_NUM_QOS_CHANNEL (4), = the hw > > exposes 32 hw QoS channels (AIROHA_NUM_TX_RING). Here we are just clear= ing the > > configuration, so I guess the current implementation is correct. >=20 > Hi Lorenzo, >=20 > You are right that there is no functional impact, and I agree this > should not go to net. Let me explain the register layout I was worried > about, and you can decide whether it is worth a net-next cleanup or > should just be dropped. >=20 > The two macros are: >=20 > REG_QUEUE_CLOSE_CFG(_n) =3D 0x00a0 + ((_n) & 0xfc) > TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) =3D BIT((_m) + (((_n) & 0x3) << 3)) >=20 > REG_QUEUE_CLOSE_CFG() masks the channel with 0xfc, and the bit macro > folds the channel with & 0x3 (mod 4) shifted by 3. So one 32-bit > register holds 4 channels x 8 queues, 8 queue bits per channel: >=20 > channel 0 -> reg 0x00a0, bits 0..7 > channel 1 -> reg 0x00a0, bits 8..15 > channel 2 -> reg 0x00a0, bits 16..23 > channel 3 -> reg 0x00a0, bits 24..31 > channel 4 -> reg 0x00a4, bits 0..7 > ... >=20 > In airoha_qdma_set_chan_tx_sched() the loop variable 'i' is passed as > the *queue* argument _m, not as a channel: >=20 > for (i =3D 0; i < AIROHA_NUM_TX_RING; i++) // i =3D 0..31 > airoha_qdma_clear(qdma, REG_QUEUE_CLOSE_CFG(channel), > TXQ_DISABLE_CHAN_QUEUE_MASK(channel, i)); >=20 > Since each channel only has AIROHA_NUM_QOS_QUEUES (8) queues, the correct > logic is to clear the 8 queue bits belonging to 'channel'. With i running > up to 31 the BIT() shift instead walks past those 8 bits and into the bit > ranges of the other channels folded into the same register. For channel 0 > the accumulated mask becomes 0xffffffff, i.e. it touches channels 1..3 as > well. >=20 > This is harmless today only because REG_QUEUE_CLOSE_CFG is written > exclusively here, via airoha_qdma_clear() (RMW clear), and the register > resets to 0 and is never set anywhere -- so clearing extra bits is a > no-op. Functionally the current code is fine, as you say. >=20 > The point is just the loop-bound semantics: 'i' is a per-channel queue > index, so the bound should be AIROHA_NUM_QOS_QUEUES (8), not > AIROHA_NUM_TX_RING (32). The two happen to be related (32 =3D=3D 4 channe= ls * > 8 queues) but mean different things. >=20 > Since there is no functional change, feel free to drop this if you would > rather not carry a cosmetic patch. If you think the clarity is worth it I > can resend against net-next without the Fixes tag. >=20 > Thanks, > Wayen >=20 Sorry you are right, I misread the code, your patch is correct. Since as you pointed out REG_QUEUE_CLOSE_CFG() is actually never set at the moment and t= he default register value is 0, I would repost this patch for net-next as soon= as it is opened (this will avoid merge conflicts). Regards, Lorenzo --VyUTMvxzWiaGc/iq Content-Type: application/pgp-signature; name=signature.asc -----BEGIN PGP SIGNATURE----- iHUEABYKAB0WIQTquNwa3Txd3rGGn7Y6cBh0uS2trAUCajJmHwAKCRA6cBh0uS2t rFNyAP9PkgQvfxp6CioRi0IbaYkDxw09bkje9eUMjIyNtTw65AEAnUSecAOlA8Ng x0S8I6Vr7K3l5fdREJxsd22doNsKKwY= =kBNZ -----END PGP SIGNATURE----- --VyUTMvxzWiaGc/iq--