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Sun, 21 Jun 2026 23:44:56 -0700 (PDT) Received: from blinky ([2601:647:6700:64d0::92d1]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-30c1bd8d78esm8370076eec.18.2026.06.21.23.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Jun 2026 23:44:55 -0700 (PDT) Date: Sun, 21 Jun 2026 23:44:52 -0700 From: Charlie Jenkins To: Atish Patra Cc: James Clark , Rob Herring , Arnaldo Carvalho de Melo , Jiri Olsa , Will Deacon , Mark Rutland , Anup Patel , Namhyung Kim , Paul Walmsley , Krzysztof Kozlowski , Ian Rogers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v6 17/21] RISC-V: perf: Add Qemu virt machine events Message-ID: References: <20260608-counter_delegation-v6-0-285b72ed65a9@meta.com> <20260608-counter_delegation-v6-17-285b72ed65a9@meta.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260608-counter_delegation-v6-17-285b72ed65a9@meta.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260621_234457_620012_A4F15FD4 X-CRM114-Status: GOOD ( 23.46 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Jun 08, 2026 at 11:01:31PM -0700, Atish Patra wrote: > From: Atish Patra > > Qemu virt machine supports a very minimal set of legacy perf events. > Add them to the vendor table so that users can use them when > counter delegation is enabled. > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/vendorid_list.h | 4 ++++ > drivers/perf/riscv_pmu_sbi.c | 36 ++++++++++++++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h > index 7f5030ee1fcf..603aa2b21c0b 100644 > --- a/arch/riscv/include/asm/vendorid_list.h > +++ b/arch/riscv/include/asm/vendorid_list.h > @@ -11,4 +11,8 @@ > #define SIFIVE_VENDOR_ID 0x489 > #define THEAD_VENDOR_ID 0x5b7 > > +#define QEMU_VIRT_VENDOR_ID 0x000 > +#define QEMU_VIRT_IMPL_ID 0x000 > +#define QEMU_VIRT_ARCH_ID 0x000 Palmer proposed a change to this a while ago to set the archid for qemu as 42 but it looks like it was never merged in qemu, but it was merged into the riscv spec. Here is the spec PR: https://github.com/riscv/riscv-isa-manual/pull/1213 Here is the current spec: https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md Here is the QEMU patch: https://lore.kernel.org/all/20240131182430.20174-1-palmer@rivosinc.com/ Should we follow up with this/maybe this should be accounted for here as an alternate id? - Charlie > + > #endif > diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c > index 00b84b28117a..74acac54328e 100644 > --- a/drivers/perf/riscv_pmu_sbi.c > +++ b/drivers/perf/riscv_pmu_sbi.c > @@ -26,6 +26,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -453,7 +454,42 @@ struct riscv_vendor_pmu_events { > .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map, \ > .attrs_events = _attrs }, > > +/* QEMU virt PMU events */ > +static const struct riscv_pmu_event qemu_virt_hw_event_map[PERF_COUNT_HW_MAX] = { > + PERF_MAP_ALL_UNSUPPORTED, > + [PERF_COUNT_HW_CPU_CYCLES] = {0x01, 0xFFFFFFF8}, > + [PERF_COUNT_HW_INSTRUCTIONS] = {0x02, 0xFFFFFFF8} > +}; > + > +static const struct riscv_pmu_event qemu_virt_cache_event_map[PERF_COUNT_HW_CACHE_MAX] > + [PERF_COUNT_HW_CACHE_OP_MAX] > + [PERF_COUNT_HW_CACHE_RESULT_MAX] = { > + PERF_CACHE_MAP_ALL_UNSUPPORTED, > + [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10019, 0xFFFFFFF8}, > + [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = {0x1001B, 0xFFFFFFF8}, > + > + [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = {0x10021, 0xFFFFFFF8}, > +}; > + > +RVPMU_EVENT_CMASK_ATTR(cycles, cycles, 0x01, 0xFFFFFFF8); > +RVPMU_EVENT_CMASK_ATTR(instructions, instructions, 0x02, 0xFFFFFFF8); > +RVPMU_EVENT_CMASK_ATTR(dTLB-load-misses, dTLB_load_miss, 0x10019, 0xFFFFFFF8); > +RVPMU_EVENT_CMASK_ATTR(dTLB-store-misses, dTLB_store_miss, 0x1001B, 0xFFFFFFF8); > +RVPMU_EVENT_CMASK_ATTR(iTLB-load-misses, iTLB_load_miss, 0x10021, 0xFFFFFFF8); > + > +static struct attribute *qemu_virt_event_group[] = { > + RVPMU_EVENT_ATTR_PTR(cycles), > + RVPMU_EVENT_ATTR_PTR(instructions), > + RVPMU_EVENT_ATTR_PTR(dTLB_load_miss), > + RVPMU_EVENT_ATTR_PTR(dTLB_store_miss), > + RVPMU_EVENT_ATTR_PTR(iTLB_load_miss), > + NULL, > +}; > + > static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { > + RISCV_VENDOR_PMU_EVENTS(QEMU_VIRT_VENDOR_ID, QEMU_VIRT_ARCH_ID, QEMU_VIRT_IMPL_ID, > + qemu_virt_hw_event_map, qemu_virt_cache_event_map, > + qemu_virt_event_group) > }; > > static const struct riscv_pmu_event *current_pmu_hw_event_map; > > -- > 2.53.0-Meta > >